Abstract: A semiconductor power module includes an electrically conductive carrier plate, a power semiconductor chip arranged on the carrier plate and electrically connected to the carrier plate, and a contact pin electrically connected to the carrier plate and forming an outer contact of the semiconductor power module. The contact pin is arranged above a soldering point. The soldering point is configured to mechanically directly or indirectly fix the contact pin on the carrier plate and to electrically connect the contact pin to the carrier plate. The contact pin is electrically connected to the carrier plate via a further connection. The further connection has a portion which is mechanically flexible in relation to the carrier plate.

Abstract: A method may include pressing a sensor module onto a control board such that the sensor module is at an initial position where an air gap is present between a module body of the sensor module and the control board such that compliant pins of the sensor module are partially inserted into the control board. The method may include mounting the control board on a power module to cause pins of the power module to be at least partially inserted into the control board and the sensor module to be at least partially inserted in the power module such that a protrusion is through an opening in a busbar. The method may include pressing the control board onto the power module to cause the pins of the power module to be further inserted into the control board, the sensor module to be further inserted in the power module, and the sensor module to be at a final position.

Abstract: A power semiconductor module includes: a carrier; a plurality of semiconductor dies attached to a first side of the carrier and electrically connected to form a circuit or part of a circuit; a cooling device at a second side of the carrier opposite the first side; a clamping device attached to the cooling device and pressing the carrier toward the cooling device such that the second side of the carrier is in thermal contact with the cooling device without having an intervening base plate between the carrier and the cooling device; and a first sensor device embedded in the clamping device or attached to an interior surface of the clamping device.

Abstract: A circuit board includes an electrically insulating part and an electrically conductive part. At least one semiconductor chip is embedded into the electrically insulating part in a part of the circuit board. Through openings in the part of the circuit board provide for passage of a cooling liquid. The through openings extend from a first surface of the circuit board to a second surface of the circuit board. The electrically conductive part includes a first outer conductive layer on the first surface and a second outer conductive layer on the second surface. The electrically conductive part also includes a first inner conductive layer which is electrically connected to the semiconductor chip. The first inner conductive layer is electrically insulated from the first outer conductive layer and from the second outer conductive layer by the electrically insulating part in the part of the circuit board.

Abstract: A capacitor includes an electrically insulating housing that encloses an interior volume, first and second conductive connection pads that are each configured as externally accessible points of electrical contact to internal electrodes of the capacitor that are disposed within the housing, and an active capacitor dielectric material disposed within the housing and being configured as a dielectric medium between the internal electrodes, the first conductive connection pad having a first planar contact surface that is substantially parallel to a first sidewall of the housing, the second conductive connection pad having a second planar contact surface that is substantially parallel to the first sidewall, the first and second planar contact surfaces being offset from one another in a direction that is orthogonal to the first sidewall.

Abstract: A capacitor includes an electrically insulating housing that encloses an interior volume, first and second conductive connection pads that are each configured as externally accessible points of electrical contact to internal electrodes of the capacitor that are disposed within the housing, and an active capacitor dielectric material disposed within the housing and being configured as a dielectric medium between the internal electrodes, the first conductive connection pad having a first planar contact surface that is substantially parallel to a first sidewall of the housing, the second conductive connection pad having a second planar contact surface that is substantially parallel to the first sidewall, the first and second planar contact surfaces being offset from one another in a direction that is orthogonal to the first sidewall.

Abstract: In accordance with an embodiment, a method includes: monitoring a temperature difference between two double-side cooled (DSC) power modules of a plurality of DSC power modules arranged in stacks of DSC power modules; comparing the temperature difference with a first temperature threshold; detecting a cooling pipe system blockage when the temperature difference is above the first temperature threshold; and after detecting the cooling pipe system blockage, disabling gate driver circuits coupled to the plurality of DSC power modules or operating the DSC power modules in a low-power mode. Each stack includes a plurality of DSC power modules. Each DSC power module has a top surface and a bottom surface, which are each thermally coupled with one or more cooling channels of a cooling pipe system. The two DSC power modules are thermally coupled with a same cooling channel of the one or more cooling channels.

Abstract: A semiconductor package includes a semiconductor module, a first package extension frame, a second package extension frame, and a plurality of fasteners. The semiconductor module includes a first side surface, a second side surface, a first major surface, and a second major surface on an opposite side of the semiconductor module from the first major surface. The first package extension frame is configured to attach to the first side surface. The second package extension frame is configured to attach to the second side surface. The plurality of fasteners are configured to mechanically couple the first package extension frame and the second package extension frame to one or more of a circuit board arranged on the first major surface and/or a heat sink arranged on the second major surface.

Abstract: A circuit board includes an electrically insulating part and an electrically conductive part. At least one semiconductor chip is embedded into the electrically insulating part in a part of the circuit board. Through openings in the part of the circuit board provide for passage of a cooling liquid. The through openings extend from a first surface of the circuit board to a second surface of the circuit board. The electrically conductive part includes a first outer conductive layer on the first surface and a second outer conductive layer on the second surface. The electrically conductive part also includes a first inner conductive layer which is electrically connected to the semiconductor chip. The first inner conductive layer is electrically insulated from the first outer conductive layer and from the second outer conductive layer by the electrically insulating part in the part of the circuit board.

Abstract: A semiconductor package includes a semiconductor module, a first package extension frame, a second package extension frame, and a plurality of fasteners. The semiconductor module includes a first side surface, a second side surface, a first major surface, and a second major surface on an opposite side of the semiconductor module from the first major surface. The first package extension frame is configured to attach to the first side surface. The second package extension frame is configured to attach to the second side surface. The plurality of fasteners are configured to mechanically couple the first package extension frame and the second package extension frame to one or more of a circuit board arranged on the first major surface and/or a heat sink arranged on the second major surface.

Abstract: A semiconductor power module includes an electrically conductive carrier plate, a power semiconductor chip arranged on the carrier plate and electrically connected to the carrier plate, and a contact pin electrically connected to the carrier plate and forming an outer contact of the semiconductor power module. The contact pin is arranged above a soldering point. The soldering point is configured to mechanically directly or indirectly fix the contact pin on the carrier plate and to electrically connect the contact pin to the carrier plate. The contact pin is electrically connected to the carrier plate via a further connection. The further connection has a portion which is mechanically flexible in relation to the carrier plate.

Abstract: A semiconductor device includes a plurality of forward conducting insulated-gate bipolar transistor cells configured to conduct a current in a forward operating mode of the semiconductor device and to block a current in a reverse operating mode of the semiconductor device. The semiconductor device also includes a plurality of reverse conducting insulated-gate bipolar transistor cells configured to conduct a current both in the forward operating mode and in the reverse operating mode. A corresponding method for operating a semiconductor device is also disclosed.

Abstract: An integrated circuit comprises a power switch comprising a current path and a current sense node; and a temperature sense circuit internally coupled between the current path and the current sense node.

Abstract: In accordance with an embodiment, a method includes: monitoring a temperature difference between two double-side cooled (DSC) power modules of a plurality of DSC power modules arranged in stacks of DSC power modules; comparing the temperature difference with a first temperature threshold; detecting a cooling pipe system blockage when the temperature difference is above the first temperature threshold; and after detecting the cooling pipe system blockage, disabling gate driver circuits coupled to the plurality of DSC power modules or operating the DSC power modules in a low-power mode. Each stack includes a plurality of DSC power modules. Each DSC power module has a top surface and a bottom surface, which are each thermally coupled with one or more cooling channels of a cooling pipe system. The two DSC power modules are thermally coupled with a same cooling channel of the one or more cooling channels.

Abstract: A semiconductor device includes a plurality of forward conducting insulated-gate bipolar transistor cells configured to conduct a current in a forward operating mode of the semiconductor device and to block a current in a reverse operating mode of the semiconductor device. The semiconductor device also includes a plurality of reverse conducting insulated-gate bipolar transistor cells configured to conduct a current both in the forward operating mode and in the reverse operating mode. A corresponding method for operating a semiconductor device is also disclosed.

Abstract: A description is given of a method for the pulsed control of a transistor which has a control terminal and a load path. The load path of the transistor is connected in series with a load. A control circuit is provided for a transistor. In the method, the transistor is controlled with a control pulse of a first type, which has a first control level at least for a first time duration, before a control pulse of a second type, which has a second control level, which is higher in comparison with the first control level. A voltage across the load path of the transistor is evaluated and the pulsed control is terminated if the voltage across the load path exceeds a predefined threshold value.

Abstract: A description is given of a method for the pulsed control of a transistor which has a control terminal and a load path. The load path of the transistor is connected in series with a load. A control circuit is provided for a transistor. In the method, the transistor is controlled with a control pulse of a first type, which has a first control level at least for a first time duration, before a control pulse of a second type, which has a second control level, which is higher in comparison with the first control level. A voltage across the load path of the transistor is evaluated and the pulsed control is terminated if the voltage across the load path exceeds a predefined threshold value.