Patents by Inventor TOMASZ KANTECKI
TOMASZ KANTECKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113863Abstract: Methods and apparatus relating to an efficient implementation of ZUC authentication are described. In one embodiment, a processor computes a tag update, based at least in part on stored data, for an authentication operation. The tag update is computed by replacing a ‘for’ loop with a carry-less multiply operation. Other embodiments are also claimed and disclosed.Type: ApplicationFiled: March 31, 2023Publication date: April 4, 2024Applicant: Intel CorporationInventors: Pablo De Lara Guarch, Tomasz Kantecki, Krystian Matusiewicz, Wajdi Feghali, Vinodh Gopal, James D. Guilford
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Publication number: 20240089206Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Patrick CONNOR, Andrey CHILIKIN, Brendan RYAN, Chris MACNAMARA, John J. BROWNE, Krishnamurthy JAMBUR SATHYANARAYANA, Stephen DOYLE, Tomasz KANTECKI, Anthony KELLY, Ciara LOFTUS, Fiona TRAHE
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Publication number: 20240048543Abstract: An apparatus includes an interface to memory, and a processor to execute one or more instructions. The instructions cause the processor to receive, via an application programming interface (API), a plurality of packets, respective packets of the plurality of packets comprising a respective header and a respective payload. Further, the instructions cause the processor to determine, by a QUIC protocol stack, to encrypt the plurality of packets in parallel. Further, the instructions cause the processor to encrypt the payloads of the plurality of packets in parallel. Further, the instructions cause the processor to encrypt the headers of the plurality of packets in parallel.Type: ApplicationFiled: August 24, 2023Publication date: February 8, 2024Applicant: Intel CorporationInventors: Ping Yu, Tomasz Kantecki, Chao Dou, Pablo De Lara Guarch, Brian Will
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Publication number: 20240028341Abstract: Examples described herein relate to a non-transitory computer-readable medium comprising instructions, that if executed by circuitry, cause the circuitry to: configure circuitry to perform cryptographic operations on packets based on Advanced Encryption Standard with Galois/Counter Mode (AES-GCM) hash (GHASH), wherein the cryptographic operations comprise a reduction operation and wherein the reduction operation comprises a single Galois territory multiplication 64 bit operation. The circuitry can include one or more of: a central processing unit (CPU), CPU-executed microcode, an accelerator, or a network interface device.Type: ApplicationFiled: September 30, 2023Publication date: January 25, 2024Inventors: Erdinc OZTURK, Kirk S. YAP, Tomasz KANTECKI
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Patent number: 11855897Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.Type: GrantFiled: June 23, 2021Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Patrick Connor, Andrey Chilikin, Brendan Ryan, Chris MacNamara, John J. Browne, Krishnamurthy Jambur Sathyanarayana, Stephen Doyle, Tomasz Kantecki, Anthony Kelly, Ciara Loftus, Fiona Trahe
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Publication number: 20230412459Abstract: Technologies for dynamically selecting resources for virtual switching include a computing device configured to identify a present demand on processing resources of the computing device that are configured to process data associated with network packets received by the computing device. Additionally, the computing device is configured to determine a present capacity of one or more acceleration resources of the computing device and configure the virtual switch based on the present demand and the present capacity of the acceleration resources. Other embodiments are described herein.Type: ApplicationFiled: September 1, 2023Publication date: December 21, 2023Inventors: Ciara Loftus, Chris MacNamara, John J. Browne, Patrick Fleming, Tomasz Kantecki, John BARRY, Patrick Connor
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Publication number: 20230401037Abstract: Methods and apparatus for optimization techniques for modular multiplication algorithms. The optimization techniques may be applied to variants of modular multiplication algorithms, including variants of Montgomery multiplication algorithms and Barrett multiplication algorithms. The optimization techniques reduce the number of serial steps in Montgomery reduction and Barrett reduction. Modular multiplication operations involving products of integer inputs A and B may be performed in parallel to obtain a value C that is reduced to a residual RES. Modular multiplication and modular reduction operations may be performed in parallel. The number of serial steps in the modular reductions are reduced to L, where L serial steps, where w is a digit size in bits, and L is a number of digits of operands=[k/w].Type: ApplicationFiled: August 24, 2023Publication date: December 14, 2023Inventors: Erdinc OZTURK, Kirk S. YAP, Tomasz KANTECKI
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Patent number: 11805065Abstract: Packets are differentiated based on their traffic class. A traffic class is allocated bandwidth for transmission. One or more core or thread can be allocated to process packets of a traffic class for transmission based on allocated bandwidth for that traffic class. If multiple traffic classes are allocated bandwidth, and a traffic class underutilizes allocated bandwidth or a traffic class is allocated insufficient bandwidth, then allocated bandwidth can be adjusted for a future transmission time slot. For example, a higher priority traffic class with excess bandwidth can share the excess bandwidth with a next highest priority traffic class for use to allocate packets for transmission for the same time slot.Type: GrantFiled: February 27, 2019Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Jasvinder Singh, John J. Browne, Tomasz Kantecki, Chris Macnamara
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Publication number: 20230342458Abstract: Examples include techniques to mitigate or prevent cache-based side-channel attacks to a cache. Examples include use of assigned class of service (COS) assigned to cores of a process to determine whether to notify an OS of a potential malicious application attempting to access a cache line cached to a processor cache. Examples also include marking pages in an application memory address space of a processor cache as unflushable to prevent a potentially malicious application from accessing sensitive data loaded to the application memory address space of the processor cache.Type: ApplicationFiled: June 27, 2023Publication date: October 26, 2023Inventors: Marcel CORNU, Tomasz KANTECKI, John J. BROWNE
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Patent number: 11671382Abstract: Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.Type: GrantFiled: June 17, 2016Date of Patent: June 6, 2023Assignee: Intel CorporationInventors: John J. Browne, Seán Harte, Tomasz Kantecki, Pierre Laurent, Chris MacNamara
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Patent number: 11630693Abstract: Technologies for power-aware scheduling include a computing device that receives network packets. The computing device classifies the network packets by priority level and then assigns each network packet to a performance group bin. The packets are assigned based on priority level and other performance criteria. The computing device schedules the network packets assigned to each performance group for processing by a processing engine such as a processor core. Network packets assigned to performance groups having a high priority level are scheduled for processing by processing engines with a high performance level. The computing device may select performance levels for processing engines based on processing workload of the network packets. The computing device may control the performance level of the processing engines, for example by controlling the frequency of processor cores. The processing workload may include packet encryption. Other embodiments are described and claimed.Type: GrantFiled: April 12, 2018Date of Patent: April 18, 2023Assignee: Intel CorporationInventors: John Browne, Chris MacNamara, Tomasz Kantecki, Peter McCarthy, Liang Ma, Mairtin O'Loingsigh, Rory Sexton, John Griffin, Nemanja Marjanovic, David Hunt
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Patent number: 11567556Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).Type: GrantFiled: March 27, 2020Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Chris Macnamara, John J. Browne, Tomasz Kantecki, David Hunt, Anatoly Burakov, Srihari Makineni, Nikhil Gupta, Ankush Varma, Dorit Shapira, Vasudevan Srinivasan, Bryan T. Butters, Shrikant M. Shah
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Publication number: 20230027516Abstract: A processor-to-processor agent to provide connectivity over a processor-to-processor interconnect between services/network functions on different processors on a same compute node in a server is provided. The processor-to-processor agent can intercept socket interface calls using a network traffic filter in the network stack and redirect the packets based on traffic matching rules.Type: ApplicationFiled: September 30, 2022Publication date: January 26, 2023Inventors: Tomasz KANTECKI, Paul HOUGH, David CREMINS, Ciara LOFTUS, Aman Deep SINGH, John J. BROWNE, David HUNT, Maksim LUKOSHKOV, Amruta MISRA, Nirint SHAH, Chris MACNAMARA
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Patent number: 11418495Abstract: Techniques and apparatuses for processing data unit are described. In one embodiment, for example, an apparatus for networking may include at least one memory, logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to access an encrypted packet having an encrypted portion, determine at least one flow control segment of the encrypted portion, decrypt the at least one flow control segment to generate a partially-decrypted packet comprising a decrypted at least one flow control segment and an encrypted remainder portion, the remainder portion comprising a portion of the encrypted packet that does not include the decrypted at least one flow control segment, access process information in the decrypted at least one flow control segment, and process the partially-decrypted packet according to the process information. Other embodiments are described and claimed.Type: GrantFiled: September 26, 2017Date of Patent: August 16, 2022Inventors: John J. Browne, Chris Macnamara, Namakkal N. Venkatesan, Tomasz Kantecki, Declan W. Doherty
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Publication number: 20220224511Abstract: Examples described herein relate to executing, on at least one processor, at least one Advanced Encryption Standard (AES) instruction, having an operation code (opcode), on operands, wherein execution of the at least one AES instruction generates an S1 box and/or S2 box of initialization and keystream generation for a SNOW3 cipher operation.Type: ApplicationFiled: March 31, 2022Publication date: July 14, 2022Inventors: Kamila LIPINSKA, Tomasz KANTECKI, Marcel CORNU, Pablo DE LARA GUARCH, Stephen MCINTYRE, Krystian MATUSIEWICZ, James GUILFORD, Vinodh GOPAL, Wajdi FEGHALI
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Publication number: 20220103345Abstract: Methods, apparatus, and software for hashing data. The methods and apparatus employ novel improvements to hash algorithms, such as a SHA-2 hash algorithm to reduce computations and increase performance. In one aspect, calculation of SHA-2 message scheduling and SHA compression operations are separated under which an SHA-2 message schedule is applied to multiple rounds of SHA compression operations over multiple chunks of data for the data item being hashed. In another aspect, the SHA-2 message schedule is implemented such that message schedules for multiple message words or data blocks are performed in parallel. The approaches may be employed to reduce hash calculations for various purposes, including generating Filecoin nodes.Type: ApplicationFiled: December 9, 2021Publication date: March 31, 2022Inventors: Tomasz KANTECKI, Wei LI, Wajdi FEGHALI, James GUILFORD, Vinodh GOPAL
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Publication number: 20210320870Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.Type: ApplicationFiled: June 23, 2021Publication date: October 14, 2021Inventors: Patrick CONNOR, Andrey CHILIKIN, Brendan RYAN, Chris MACNAMARA, John J. BROWNE, Krishnamurthy JAMBUR SATHYANARAYANA, Stephen DOYLE, Tomasz KANTECKI, Anthony KELLY, Ciara LOFTUS, Fiona TRAHE
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Patent number: 11080202Abstract: A computing apparatus, including: a processor; a pointer to a counter memory location; and a lazy increment counter engine to: receive a stimulus to update the counter; and lazy increment the counter including issuing a weakly-ordered increment directive to the pointer.Type: GrantFiled: September 30, 2017Date of Patent: August 3, 2021Assignee: Intel CorporationInventors: Niall D. McDonnell, Christopher MacNamara, John J. Browne, Andrew Cunningham, Brendan Ryan, Patrick Fleming, Namakkal N. Venkatesan, Bruce Richardson, Tomasz Kantecki, Sean Harte, Pierre Laurent
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Publication number: 20210224128Abstract: Techniques for managing workloads in processor cores are disclosed. High priority or mission critical workloads may be assigned to processor cores of a processor. When a power limited throttling condition is met, the processor may throttle some of its cores while not throttling the cores with the high priority or mission critical workloads assigned to it. Such an approach can ensure that mission critical workloads continue even upon throttling of the processor cores.Type: ApplicationFiled: December 24, 2020Publication date: July 22, 2021Applicant: Intel CorporationInventors: Chris M. MacNamara, John J. Browne, Amruta Misra, Niall C. Power, Dave Cremins, Tomasz Kantecki, Paul Hough, Killian Muldoon
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Patent number: 11070476Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.Type: GrantFiled: April 26, 2019Date of Patent: July 20, 2021Assignee: Intel CorporationInventors: Patrick Connor, Andrey Chilikin, Brendan Ryan, Chris MacNamara, John J. Browne, Krishnamurthy Jambur Sathyanarayana, Stephen Doyle, Tomasz Kantecki, Anthony Kelly, Ciara Loftus, Fiona Trahe