Patents by Inventor TOMASZ KANTECKI
TOMASZ KANTECKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10341264Abstract: Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.Type: GrantFiled: June 30, 2016Date of Patent: July 2, 2019Assignee: Intel CorporationInventors: John J. Browne, Tomasz Kantecki, Chris MacNamara, Pierre Laurent, Sean Harte
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Publication number: 20190199646Abstract: Packets are differentiated based on their traffic class. A traffic class is allocated bandwidth for transmission. One or more core or thread can be allocated to process packets of a traffic class for transmission based on allocated bandwidth for that traffic class. If multiple traffic classes are allocated bandwidth, and a traffic class underutilizes allocated bandwidth or a traffic class is allocated insufficient bandwidth, then allocated bandwidth can be adjusted for a future transmission time slot. For example, a higher priority traffic class with excess bandwidth can share the excess bandwidth with a next highest priority traffic class for use to allocate packets for transmission for the same time slot.Type: ApplicationFiled: February 27, 2019Publication date: June 27, 2019Inventors: Jasvinder SINGH, John J. BROWNE, Tomasz KANTECKI, Chris MACNAMARA
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Patent number: 10331590Abstract: Discloses is an apparatus including a network interface controller (NIC), memory, and an accelerator. The accelerator can include a direct memory access (DMA) controller configured to receive data packets from the NIC and to provide the data packets to the memory. The accelerator can also include processing circuitry to generate processed data packets by implementing packet processing functions on the data packets received from the NIC, and to provide the processed data packets to at least one processing core. Other methods, apparatuses, articles and systems are also described.Type: GrantFiled: June 30, 2016Date of Patent: June 25, 2019Assignee: Intel CorporationInventors: Chris MacNamara, Tomasz Kantecki, John J. Browne
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Publication number: 20190163630Abstract: Systems and methods for tracking cache line consumption. An example system may comprise: a cache comprising a plurality of cache entries for storing a plurality of cache lines; a processing core, operatively coupled to the cache; and a cache control logic, to: responsive to detecting an update operation with respect to a cache line of the plurality of cache lines, set a cache line access tracking flag associated with the cache line to a first state indicating that the cache line has been produced; and responsive to detecting a read operation with respect to the cache line, set the cache line access tracking flag associated with the cache line to a second state indicating that the cache line has been consumed.Type: ApplicationFiled: November 27, 2017Publication date: May 30, 2019Inventors: Mark Gray, Tomasz Kantecki
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Publication number: 20190155645Abstract: Packets received at an input port can be sub-divided into timeslots. A core or thread can process packets associated with a timeslot. The timeslot size can be increased or decreased based on utilization of a core that is allocated to process packets associated with a timeslot. A timeslot number can be assigned to each received packet. For transmission of the received packets, the timeslot number can be used to maintain an order of transmission to attempt to reduce out-of-order packet transmission.Type: ApplicationFiled: January 23, 2019Publication date: May 23, 2019Inventors: John J. BROWNE, Chris MACNAMARA, Tomasz KANTECKI
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Publication number: 20190102312Abstract: A computing apparatus, including: a processor; a pointer to a counter memory location; and a lazy increment counter engine to: receive a stimulus to update the counter; and lazy increment the counter including issuing a weakly-ordered increment directive to the pointer.Type: ApplicationFiled: September 30, 2017Publication date: April 4, 2019Inventors: Niall D. McDonnell, Christopher MacNamara, John J. Browne, Andrew Cunningham, Brendan Ryan, Patrick Fleming, Namakkal N. Venkatesan, Bruce Richardson, Tomasz Kantecki, Sean Harte, Pierre Laurent
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Publication number: 20190097951Abstract: A network interface device, including: an ingress interface; a host platform interface to communicatively couple to a host platform; and a packet preprocessor including logic to: receive via the ingress interface a data sequence including a plurality of discrete data units; identify the data sequence as data for a parallel processing operation; reorder the discrete data units into a reordered data frame, the reordered data frame configured to order the discrete data units for consumption by the parallel operation; and send the reordered data to the host platform via the host platform interface.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Applicant: Intel CorporationInventors: Tomasz Kantecki, Niall Power, John J. Browne, Christopher MacNamara, Stephen Doyle
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Publication number: 20190097984Abstract: Techniques and apparatuses for processing data unit are described. In one embodiment, for example, an apparatus for networking may include at least one memory, logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to access an encrypted packet having an encrypted portion, determine at least one flow control segment of the encrypted portion, decrypt the at least one flow control segment to generate a partially-decrypted packet comprising a decrypted at least one flow control segment and an encrypted remainder portion, the remainder portion comprising a portion of the encrypted packet that does not include the decrypted at least one flow control segment, access process information in the decrypted at least one flow control segment, and process the partially-decrypted packet according to the process information. Other embodiments are described and claimed.Type: ApplicationFiled: September 26, 2017Publication date: March 28, 2019Applicant: INTEL CORPORATIONInventors: John J. Browne, Chris Macnamara, Namakkal N. Venkatesan, Tomasz Kantecki, Declan W. Doherty
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Publication number: 20190097948Abstract: An apparatus, including: a hardware platform; logic to execute on the hardware platform, the logic configured to: receive a batch including first plurality of packets; identify a common attribute of the batch; perform batch processing on the batch according to the common attribute; generate a hint for the batch, the hint comprising information about the batch to facilitate processing of the batch; and forward the batch to a host platform network interface with the hint.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Applicant: Intel CorporationInventors: John J. Browne, Christopher MacNamara, Tomasz Kantecki, Barak Hermesh, Sean Harte, Andrey Chilikin, Brendan Ryan, Bruce Richardson, Michael A. O'Hanlon, Andrew Cunningham
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Publication number: 20190044873Abstract: Examples may include an apparatus having processing logic to receive a packet, to classify the packet based at least in part on a header of the packet, to apply one or more serial packet filter rules to the packet, and when parallel packet filter rules are selected to apply one or more parallel packet filter rules to the packet, wherein application of the serial packet filter rules is performed in parallel with application of the parallel packet filter rules.Type: ApplicationFiled: June 29, 2018Publication date: February 7, 2019Inventors: John BROWNE, Chris MACNAMARA, Tomasz KANTECKI, Parthasarathy SARANGAM
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Publication number: 20190044893Abstract: Technologies for buffering received network packet data include a compute device with a network interface controller (NIC) configured to determine a packet size of a network packet received by the NIC and identify a preferred buffer size between a small buffer and a large buffer. The NIC is further configured to select, from the descriptor, a buffer pointer based on the preferred buffer size, wherein the buffer pointer comprises one of a small buffer pointer corresponding to a first physical address in memory allocated to the small buffer or a large buffer pointer corresponding to a second physical address in memory allocated to the large buffer. Additionally, the NIC is configured to store at least a portion of the network packet in the memory based on the selected buffer pointer. Other embodiments are described herein.Type: ApplicationFiled: June 30, 2018Publication date: February 7, 2019Inventors: Bruce Richardson, Chris MacNamara, Patrick Fleming, Tomasz Kantecki, Ciara Loftus, John J. Browne, Patrick Connor
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Publication number: 20190042310Abstract: Technologies for power-aware scheduling include a computing device that receives network packets. The computing device classifies the network packets by priority level and then assigns each network packet to a performance group bin. The packets are assigned based on priority level and other performance criteria. The computing device schedules the network packets assigned to each performance group for processing by a processing engine such as a processor core. Network packets assigned to performance groups having a high priority level are scheduled for processing by processing engines with a high performance level. The computing device may select performance levels for processing engines based on processing workload of the network packets. The computing device may control the performance level of the processing engines, for example by controlling the frequency of processor cores. The processing workload may include packet encryption. Other embodiments are described and claimed.Type: ApplicationFiled: April 12, 2018Publication date: February 7, 2019Inventors: John Browne, Chris MacNamara, Tomasz Kantecki, Peter McCarthy, Ma Liang, Mairtin O'Loingsigh, Rory Sexton, John Griffin, Nemanja Marjanovic, David Hunt
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Publication number: 20190042739Abstract: Technologies for cache side channel attack detection and mitigation include an analytics server and one or more monitored computing devices. The analytics server polls each computing device for analytics counter data. The computing device generates the analytics counter data using a resource manager of a processor of the computing device. The analytics counter data may include last-level cache data or memory bandwidth data. The analytics server identifies suspicious core activity based on the analytics counter data and, if identified, deploys a detection process to the computing device. The computing device executes the detection process to identify suspicious application activity. If identified, the computing device may perform one or more corrective actions. Corrective actions include limiting resource usage by a suspicious process using the resource manager of the processor. The resource manager may limit cache occupancy or memory bandwidth used by the suspicious process.Type: ApplicationFiled: June 29, 2018Publication date: February 7, 2019Inventors: John J. Browne, Marcel Cornu, Timothy Verrall, Tomasz Kantecki, Niall Power, Weigang Li, Eoin Walsh, Maryam Tahhan
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Publication number: 20190044812Abstract: Technologies for dynamically selecting resources for virtual switching include a network appliance configured to identify a present demand on processing resources of the network appliance that are configured to process data associated with network packets received by the network appliance. Additionally, the network appliance is configured to determine a present capacity of one or more acceleration resources of the network appliance and determine a virtual switch operation mode based on the present demand and the present capacity of the acceleration resources, wherein the virtual switch operation mode indicates which of the acceleration resources are to be enabled. The network appliance is additionally configured to configure a virtual switch of the network appliance to operate as a function of the determined virtual switch operation mode and assign acceleration resources of the network appliance as a function of the determined virtual switch operation mode. Other embodiments are described herein.Type: ApplicationFiled: September 13, 2018Publication date: February 7, 2019Inventors: Ciara Loftus, Chris MacNamara, John J. Browne, Patrick Fleming, Tomasz Kantecki, John Barry, Patrick Connor
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Publication number: 20190044860Abstract: Technologies for providing adaptive polling of packet queues include a compute device. The compute device includes a network interface controller and a compute engine that includes a set of cores and a memory that includes a queue to store packets received by the network interface controller. The compute engine is configured to determine a predicted time period for the queue to receive packets without overflowing, execute, during the time period and with a core that is assigned to periodically poll the queue for packets, a workload, and poll, with the assigned core, the queue to remove the packets from the queue. Other embodiments are also described and claimed.Type: ApplicationFiled: June 18, 2018Publication date: February 7, 2019Inventors: Chris MacNamara, John Browne, Tomasz Kantecki, Ciara Loftus, John Barry, Patrick Connor, Patrick Fleming
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Publication number: 20190042454Abstract: Examples include techniques to manage cache resource allocations associated with one or more cache class of service (CLOS) assignments for a processor cache. Examples include flushing portions of an allocated cache resource responsive to reassignments of CLOS.Type: ApplicationFiled: June 29, 2018Publication date: February 7, 2019Inventors: Tomasz KANTECKI, John BROWNE, Chris MACNAMARA, Timothy VERRALL, Marcel CORNU, Eoin WALSH, Andrew J. HERDRICH
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Publication number: 20190042295Abstract: Particular embodiments described herein provide for an electronic device that can be configured to receive a request for a timestamp associated with a virtual machine, determine a current time from a timestamp counter, and subtract a timing compensation from the current time from the timestamp counter to create the timestamp, where the timing compensation includes an amount of time that execution of the virtual machine was suspended. In an example, a VM_EXIT instruction was used to suspend execution of the virtual machine and the timestamp counter was read before the VM_EXIT instruction was processed by a hypervisor.Type: ApplicationFiled: June 29, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Liang Ma, John Joseph Browne, Xuebin Yang, Tomasz Kantecki, Andrew J. Herdrich
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Publication number: 20190042314Abstract: Particular embodiments described herein provide for an electronic device that can be configured to partition a resource into a plurality of partitions and allocate a reserved portion and a corresponding burst portion in each of the plurality of partitions. Each of the allocated reserved portions and corresponding burst portions are reserved for a specific component or application, where any part of the allocated burst portion not being used by the specific component or application can be used by other components and/or applications.Type: ApplicationFiled: January 12, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Timothy Verrall, John J. Browne, Tomasz Kantecki, Maryam Tahhan, Eoin Walsh, Andrew Duignan, Alan Carey, Wojciech Andralojc, Damien Power, Tarun Viswanathan
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Publication number: 20190004922Abstract: A method for monitoring health of processes includes a compute device having a performance monitoring parameter manager and an analytics engine. The compute device accesses performance monitoring parameters associated with a monitored process of the compute device. The compute device samples one or more hardware counters associated with the monitored process and applies a performance monitor filter to the sampled one or more hardware counters to generate hardware counter values. The compute device performs a process fault check on the monitored process based on the hardware counter values and the performance monitoring parameters.Type: ApplicationFiled: June 29, 2017Publication date: January 3, 2019Inventors: John J. Browne, Tomasz Kantecki, Wojciech Andralojc, Timothy Verrall, Maryam Tahhan, Eoin Walsh, Damien Power, Chris Macnamara
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Publication number: 20190007330Abstract: Technologies for network packet processing include a computing device that receives incoming network packets. The computing device adds the incoming network packets to an input lockless shared ring, and then classifies the network packets. After classification, the computing device adds the network packets to multiple lockless shared traffic class rings, with each ring associated with a traffic class and output port. The computing device may allocate bandwidth between network packets active during a scheduling quantum in the traffic class rings associated with an output port, schedule the network packets in the traffic class rings for transmission, and then transmit the network packets in response to scheduling. The computing device may perform traffic class separation in parallel with bandwidth allocation and traffic scheduling. In some embodiments, the computing device may perform bandwidth allocation and/or traffic scheduling on each traffic class ring in parallel.Type: ApplicationFiled: June 28, 2017Publication date: January 3, 2019Inventors: John J. Browne, Tomasz Kantecki, Chris Macnamara, Pierre Laurent, Sean Harte, Peter McCarthy, Jacqueline F. Jardim, Liang Ma