Abstract: A system and methods for classification of events, the system including a memory, a network interface, and a processor configured to monitor system events via the network interface and store the system events as an event log in the memory, collect information about events from various web resources, extract, from the event log and the collected event information, labeling data including data about urgency of events and generate, based on the extracted labeling data, labeling data structures ascribing labels to respective events, extract, from the event log and the collected event information, event features data and generate, based on the extracted event features data, event features data structures ascribing features to respective events, and formulate decision rule structures for identification of urgent events based on the labeling data structures and the event features data structures.

Abstract: A system and method for operating an agent. A policy may be generated based on an analysis of a code segment of an agent, analysis of the execution and/or installation of an agent. An interaction with the agent may be intercepted. The interaction may be analyzed according to the policy. A machine for performing an operation related to the interaction may be selected. A proxy on the selected machine may perform the operation and return a result to the agent. In some embodiments, a request to perform a task may be intercepted. A first portion of the task may be performed by an agent and a second portion of the task may be performed by a proxy.

Abstract: Technologies for clearing a page of memory include a memory device configured write a value to a block of memory cells in response to an activation signal. The memory device includes a row decoder responsive to a memory address to select a row of memory cells and a column decoder responsive to the activation signal to select one or more columns of memory cells. Additionally, a write driver of the memory device is configured to write a value to global input/output lines, which are connected to the selected memory cells in response to the activation signal and regardless of data received on a data input of the write driver.

Abstract: A system and methods for classification of events, the system including a memory, a network interface, and a processor configured to monitor system events via the network interface and store the system events as an event log in the memory, collect information about events from various web resources, extract, from the event log and the collected event information, labeling data including data about urgency of events and generate, based on the extracted labeling data, labeling data structures ascribing labels to respective events, extract, from the event log and the collected event information, event features data and generate, based on the extracted event features data, event features data structures ascribing features to respective events, and formulate decision rule structures for identification of urgent events based on the labeling data structures and the event features data structures.

Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

Abstract: A management unit comprising a processor, the management unit is configured to be in communication with at least one management system, the at least one management system configured to be in communication with at least one endpoint machine in an environment of multiple endpoint machines, the processor is configured to: assign for the at least one management system a dynamic group of endpoint machines; execute a relevant adaptor on the management system according to the assigned dynamic group; and apply to the dynamic group of endpoint machines, by the executed adaptor, policy rules relevant to the dynamic group of endpoint machines.

Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.

Abstract: A method and system for high speed on chip testing for quality assurance. A multi-core system on a chip has a plurality of processing cores. The cores act as transaction agents with an auto-response unit fabricated on the chip at a chip boundary, the auto-response unit to provide a deterministic return value based on a logical address of a received read request.

Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.

Abstract: Technologies for clearing a page of memory include a memory device configured write a value to a block of memory cells in response to an activation signal. The memory device includes a row decoder responsive to a memory address to select a row of memory cells and a column decoder responsive to the activation signal to select one or more columns of memory cells. Additionally, a write driver of the memory device is configured to write a value to global input/output lines, which are connected to the selected memory cells in response to the activation signal and regardless of data received on a data input of the write driver.

Abstract: A method of executing an original agent application as a virtual agent, the method comprising encapsulating an original agent in a container file to produce a virtual agent; providing the virtual agent to an endpoint machine; and executing the virtual agent, within the container, on the endpoint machine.

Abstract: Memory subsystem refresh management enables commands to access one or more identified banks across different bank groups with a single command. Instead of sending commands identifying a bank or banks in separate bank groups by each bank group individually, the command can cause the memory device to access banks in different bank groups. The command can be a refresh command. The command can be a precharge command.

Abstract: This is a hanger/drying unit that dries leather suits, race suits, wetsuits, dry suits, Hazmat suits, firemen gear, etc, in a much quicker time then air drying. This unit uses a high powerful fan to bring in air and forces it out through the outlets of the arms, chest and bottom of unit. The air is forced through the suit to dry it at a faster rate and help prevent mold, and mildew growth.

Abstract: Throttling of memory access commands. Accesses to rows of a memory device are monitored for a timeframe. The timeframe is divided into at least two sub-frames. If the number of accesses for any of the rows during a first sub-frame exceeds a first threshold throttling accesses to the accessed row at a first rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the first threshold. The first threshold is associated with risk of data corruption on a row physically adjacent to the accessed row. If a number of accesses for the accessed row during a second sub-frame exceeds a second threshold, throttling accesses to the accessed row at a second rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the second threshold. The second threshold is greater than the first threshold. The second throttling rate is greater than the first throttling rate.

Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.

Abstract: A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.

Abstract: A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.

Abstract: A dynamic priority controller monitors a level of data in a display engine buffer and compares the level of data in the display engine buffer to a plurality of thresholds including a first threshold and a second threshold. When the level of data in the display engine buffer is less than or equal to the first threshold, the dynamic priority controller increases a priority for processing display engine data in a communication channel. When the level of data in the display engine buffer is greater than or equal to the second threshold, the dynamic priority controller decreases the priority for processing the display engine data in the communication channel.

Abstract: Throttling of memory access commands. Accesses to rows of a memory device are monitored for a timeframe. The timeframe is divided into at least two sub-frames. If the number of accesses for any of the rows during a first sub-frame exceeds a first threshold throttling accesses to the accessed row at a first rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the first threshold. The first threshold is associated with risk of data corruption on a row physically adjacent to the accessed row. If a number of accesses for the accessed row during a second sub-frame exceeds a second threshold, throttling accesses to the accessed row at a second rate. Not throttling accesses to the accessed row if the number of accesses to the accessed row does not exceed the second threshold. The second threshold is greater than the first threshold. The second throttling rate is greater than the first throttling rate.