Patents by Inventor Tomio Nakano

Tomio Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4660174
    Abstract: In a semiconductor memory device including word lines (WL) and bit lines (BL), a regular pattern circuit area comprising elements regularly arranged in line with the word lines and/or the bit lines is divided into a plurality of blocks (1-1, 1-2). Provided between the divided blocks are irregular or peripheral circuit areas (2). Provided outside of the divided blocks are pads (P.sub.1 to P.sub.16).
    Type: Grant
    Filed: June 28, 1984
    Date of Patent: April 21, 1987
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Tomio Nakano, Kimiaki Sato
  • Patent number: 4649289
    Abstract: A circuit for maintaining the potential of a node of a MOS dynamic circuit using a repetitive charging circuit to hold the potential higher than a source voltage without supplying a steady current to the node. The potential is maintained until a reset signal is applied to the MOS dynamic circuit.
    Type: Grant
    Filed: December 17, 1984
    Date of Patent: March 10, 1987
    Assignee: Fujitsu Limited
    Inventor: Tomio Nakano
  • Patent number: 4649406
    Abstract: In a semiconductor memory device having stacked capacitor-type memory cells, the capacitor of each memory cell includes a base electrode, an insulating layer, and a counter electrode. The base electrode of each memory cell is partly superposed without contact on the base electrodes of other adjacent memory cells.
    Type: Grant
    Filed: June 12, 1984
    Date of Patent: March 10, 1987
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Tomio Nakano, Kimiaki Sato
  • Patent number: 4641166
    Abstract: In a semiconductor memory device having stacked capacitor-type memory cells, the capacitor of each memory cell comprises an electrode, an insulating layer, and a counter electrode. The electrode is connected electrically to a source or drain region of a transfer transistor and extends over a part of a word line adjacent to another word line serving a gate electrode of the transfer transistor, at which part no memory cell is formed.
    Type: Grant
    Filed: December 12, 1983
    Date of Patent: February 3, 1987
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Tomio Nakano, Kimiaki Sato
  • Patent number: 4636982
    Abstract: A semiconductor memory device including at least two groups, each of said groups including a plurality of memory cell array blocks. The number of the memory cell array blocks which are activated in one group is made different from the number of memory cell array blocks which are activated in another group by providing a sequential circuit, thus reducing the maximum power consumption.
    Type: Grant
    Filed: May 1, 1985
    Date of Patent: January 13, 1987
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Tomio Nakano, Kimiaki Sato
  • Patent number: 4601017
    Abstract: A semiconductor memory device comprises active pull-up circuits (APU.sub.1, APU.sub.2) each provided for one bit line (BL.sub.1, BL.sub.1). Each active pull-up circuit (APU.sub.1) has connections to two bit lines. That is, an active pull-up circuit (APU.sub.1) for a first bit line (BL.sub.1) comprises a first transistor (Q.sub.1) connected between a power supply terminal (V.sub.CC) and the first bit line, a second transistor (Q.sub.2) connected between the gate of the first transistor and the first bit line, and a capacitor (C.sub.1) connected to the gate of the first transistor. The gate of the second transistor is connected to a second bit line (BL.sub.1) which is paired with the first bit line. The capacitor receives an active pull-up signal (.phi..sub.AP). A circuit (Q.sub.3, Q.sub.4, Q.sub.5) is provided for transmitting a high level potential to the gate (N.sub.1) of the first transistor to precharge the capacitor.
    Type: Grant
    Filed: December 15, 1983
    Date of Patent: July 15, 1986
    Assignee: Fujitsu Limited
    Inventors: Hirohiko Mochizuki, Yoshihiro Takemae, Tomio Nakano, Kimiaki Sato
  • Patent number: 4597059
    Abstract: A dynamic semiconductor memory device comprising: (1) one-transistor one-capacitor type memory cells connected between word lines and bit lines and (2) flip-flops, each flip-flop being connected between a pair of word lines to clamp an unselected word line in the pair of word lines to the low voltage of a power source, thereby preventing a subsequent erroneous reading operation as a result of an increase in potential of the unselected word line.
    Type: Grant
    Filed: September 26, 1983
    Date of Patent: June 24, 1986
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Tomio Nakano, Kimiaki Sato
  • Patent number: 4592020
    Abstract: A semiconductor memory device having clamp circuits, each of which operates reliably without being affected by the resistance of a word line. Each of the clamp circuits is connected to a corresponding word line and clamps the potential of the word line to a reference potential when it is in a non-selected condition. Each of the clamp circuits includes a flip-flop having a first terminal connected to the corresponding word line and a second terminal which receives a control signal for operating each of the clamp circuits. The control signal is applied to the second terminal when the potential of a selected word line exceeds at least the potential necessary for inverting the condition of the flip-flop.
    Type: Grant
    Filed: November 22, 1983
    Date of Patent: May 27, 1986
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Tomio Nakano, Kimiaki Sato
  • Patent number: 4592025
    Abstract: A circuit for storing information by blown and unblown fuses has at least two fuses per bit and an information output circuit. The information output circuit discriminates between the state in which all the fuses are unblown and the state in which at least one of the fuses is blown, and provides an output in accordance with the result of the discrimination as stored information.
    Type: Grant
    Filed: April 10, 1984
    Date of Patent: May 27, 1986
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Junji Ogawa, Yasuhiro Fujii, Tomio Nakano, Takeo Tatematsu, Takashi Horii, Masao Nakano, Norihisa Tsuge, deceased
  • Patent number: 4583179
    Abstract: A semiconductor integrated circuit which includes therein at least one inspection circuit for inspecting a voltage level produced at an internal node to be inspected. The inspection circuit has at least a control signal input portion connected to the internal node to be inspected and an input part connected to an external input/output pin. The inspection circuit includes a series-connected transistor and diode connected between a power source and the input portion, a capacitor connected between a gate of the transistor and the input portion, and a transfer gate transistor connected between the control signal input portion and the gate of the transistor. The inspection circuit discriminates the level at the internal node according to a flow or nonflow of a current, via the external input/output pin, when a particular signal having a voltage level higher than the power source level is supplied to the external input/output pin.
    Type: Grant
    Filed: December 29, 1982
    Date of Patent: April 15, 1986
    Assignee: Fujitsu Limited
    Inventors: Takashi Horii, Tomio Nakano, Masao Nakano, Norihisa Tsuge, Junji Ogawa
  • Patent number: 4581720
    Abstract: A dynamic memory having single element storage cells. A plurality of gate circuits are connected to the column lines of the storage cell array at both ends of the column line. A plurality of sense amplifiers are disposed along both ends of the column lines and connected to the gate circuits. In accordance with switching of the gate circuits, a portion of the sense amplifiers are coupled with a portion of the column lines to perform a refresh operation and read or write operations for the storage cells connected thereto. Also, the remaining sense amplifiers are coupled with the remaining column lines to perform only the refresh operation of the storage cells connected to the remaining column lines.
    Type: Grant
    Filed: September 26, 1983
    Date of Patent: April 8, 1986
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Tomio Nakano, Kimiaki Sato
  • Patent number: 4578781
    Abstract: An MIS transistor circuit which is operated alternately in a reset state and in an active state, comprises a voltage holding circuit for holding a power supply voltage applied in each reset state so as to provide a clamped voltage. The clamped voltage is applied during each active state to the desired nodes of the MIS transistor circuit as an actual power supply voltage, whereby error operation due to voltage fluctuation of the power supply voltage is prevented.
    Type: Grant
    Filed: August 31, 1982
    Date of Patent: March 25, 1986
    Assignee: Fujitsu Limited
    Inventors: Junji Ogawa, Tomio Nakano, Masao Nakano, Norihisa Tsuge, Takashi Horii
  • Patent number: 4578776
    Abstract: A dynamic semiconductor memory device includes a one-transistor one-capacitor type dynamic memory cell and a voltage dividing circuit having a potential providing terminal for providing an intermediate potential between the potential of the power supply and ground potential. One electrode of the capacitor in the memory cell is connected to the potential providing terminal. The voltage dividing circuit includes a potential switching circuit which changes the intermediate potential synchronously with an internal clock signal for selecting a word line, thus preventing a read error.
    Type: Grant
    Filed: November 28, 1983
    Date of Patent: March 25, 1986
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Tomio Nakano, Kimiaki Sato
  • Patent number: 4570088
    Abstract: A semiconductor device, provided with a buffer, which comprises a first transistor for pulling up the output terminal voltage, a second transistor for pulling down the output terminal voltage, and a charge-pumping circuit for maintaining the output terminal voltage at a level higher than the power source voltage by charge pumping when the output terminal voltage is at a high level. The semiconductor device further comprises a circuit for pulling down the output terminal voltage during the period from when power is supplied to when an input signal is supplied to the buffer.
    Type: Grant
    Filed: July 1, 1983
    Date of Patent: February 11, 1986
    Assignee: Fujitsu Limited
    Inventors: Shigeki Nozaki, Tomio Nakano, Katsuhiko Kabashima
  • Patent number: 4545037
    Abstract: A dynamic semiconductor memory device of an open bit-line type includes a plurality of first wiring lines running on common opposite electrodes for forming opposite electrodes of memory cell capacitors and connected to the common opposite electrodes at a number of contact points. A second wiring line is connected to the ends of the first wiring lines and to a voltage supply line at the center point of the second wiring line, so that the potential distribution of the common opposite electrodes can be equalized precisely.
    Type: Grant
    Filed: June 28, 1983
    Date of Patent: October 1, 1985
    Assignee: Fujitsu Limited
    Inventors: Tomio Nakano, Masao Nakano, Junji Ogawa
  • Patent number: 4532613
    Abstract: In a semiconductor memory device including an output buffer circuit receiving data signals read out from a memory cell array, an output stage MOS transistor being turned ON and OFF according to the output signals of the output buffer circuit, and an output buffer enable (OBE) signal generator circuit for generating an OBE signal which is used as the voltage supply to the output stage of the output buffer circuit, a V.sub.BS voltage generator circuit is provided for generating a voltage V.sub.BS higher than the voltage source V.sub.CC preceding the rising up of the OBE signal, which voltage V.sub.BS is used as a voltage supply to the output stage of the OBE signal generator circuit, whereby the OBE signal is formed as a voltage waveform which rises rapidly up to a level higher than the voltage source V.sub.CC.
    Type: Grant
    Filed: March 9, 1982
    Date of Patent: July 30, 1985
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Tomio Nakano, Tsuyoshi Ohira
  • Patent number: 4511997
    Abstract: A metal-insulator semiconductor dynamic memory device including sense amplifiers arrayed on a semiconductor substrate and divided into a plurality of sense amplifier groups. Column decoders are provided, one decoder for each sense amplifier group, each sense amplifier group being selected by the column decoder. One or more control signal lines for simultaneously selecting the output signals of at least two sense amplifiers in the sense amplifier group selected by the column decoder, a plurality of data buses for transferring the output signals of at least two sense amplifiers selected by one or more control signal lines, are included in the memory device. All of the sense amplifiers have the control signal lines and the data buses in common.
    Type: Grant
    Filed: November 5, 1982
    Date of Patent: April 16, 1985
    Assignee: Fujitsu Limited
    Inventors: Shigeki Nozaki, Yoshihiro Takemae, Tomio Nakano
  • Patent number: 4503339
    Abstract: A semiconductor device comprising a substrate voltage-generating circuit which has an oscillating circuit and a pumping circuit. The substrate voltage-generating circuit also has a control circuit for controlling the application of the output signal of the oscillating circuit to the pumping circuit and a terminal electrode for receiving an external signal to control the control circuit and to stop the application of the output signal of the oscillating circuit to the pumping circuit.
    Type: Grant
    Filed: May 5, 1982
    Date of Patent: March 5, 1985
    Assignee: Fujitsu Limited
    Inventors: Norihisa Tsuge, Tomio Nakano, Masao Nakano
  • Patent number: 4486860
    Abstract: In a dynamic random access memory device, the memory cells, sense amplifiers, word drivers, and the like are divided into a plurality of blocks. During the access mode, only one of the blocks in which a desired row exists is driven while, during the refresh mode, all of the blocks are driven.
    Type: Grant
    Filed: June 28, 1982
    Date of Patent: December 4, 1984
    Assignee: Fujitsu Limited
    Inventors: Yoshihiro Takemae, Tomio Nakano
  • Patent number: 4484312
    Abstract: A dynamic random access memory device which comprises one-transistor, one-capacitor-type memory cells (C.sub.00 .about.C.sub.127,127) in rows and columns and dummy cells (DC.sub.20 '.about.DC.sub.2,127 ', DC.sub.20 ".about.DC.sub.2,127 ", DC.sub.20 "'.about.DC.sub.2,127 "') in rows. The capacitors (C.sub.d) of the dummy cells are charged to a high power supply potential (V.sub.CC) by one or more charging transistors (Q.sub.A or Q.sub.A ') clocked by a reset clock signal (.phi..sub.R). The capacitors (C.sub.d) of the dummy cells are discharged to a low power supply potential (V.sub.SS) by one or more transistors (Q.sub.B or Q.sub.B ') clocked by an operation clock signal (.phi..sub.WL) having a potential lower than the high power supply potential (V.sub.CC).
    Type: Grant
    Filed: June 25, 1982
    Date of Patent: November 20, 1984
    Assignee: Fujitsu Limited
    Inventors: Tomio Nakano, Masao Nakano, Yoshihiro Takemae, Norihisa Tsuge, Tsuyoshi Ohira