Tomio Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A bias-voltage generator suitable for measuring a substrate leakage current is disclosed. The bias-voltage generator comprises of an oscillator, a charge-pumping circuit which is driven by the oscillator via a pumping capacitor, and a charge-pumping switch. The charge-pumping switch is connected in series with the charge-pumping circuit. The charge-pumping switch cooperates with an external electrode for controlling the ON or OFF condition of the charge pumping circuit. The charge-pumping switch is turned OFF by the external electrode becoming a floating state and a resistor employed to ensure the charge pumping switch is inoperable after the above-mentioned measurement is completed and the circuit is shipped from the factory.
Abstract: A semiconductor circuit, used as a buffer circuit, has an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit, including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during a standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit. The input stage circuit generates an output clock signal. The semiconductor circuit further comprises a circuit for applying a high level clock signal, having the same phase as the inverted clock sigal and a level higher than the level of the sum of a power source upper limit voltage and a transistor threshold voltage, to transistor gates, whereby the voltage of a point charged during the standby period corresponds to the voltage of the power source throughout the standby period.
Abstract: A semiconductor memory device has fuses coated with a protecting layer. The protecting layer is selectively etched to open windows so as to expose narrow center portions of the fuses. After the opening of the center windows, the fusing operation of the fuses is carried out to open a gap in the center window portion of the fuse material. In a preferred embodiment, another protective layer is then added to fill the gaps in the blown fuses.
Abstract: An address buffer circuit for comverting an address signal (A.sub.i) of a TTL level into an address signal (A) of a MOS level an its inverted signal (A) comprising: a pre-amplifier (P-AMP) for receiving the address signal having a TTL level; a main amplifier (M-AMP) comprising a flip-flop (FF.sub.3), a circuit for defining the operation of the flip-flop (FF.sub.3); and an output circuit (OUT) comprised of another flip-flop (FF.sub.4) for producing the address signals of a MOS level. In the pre-amplifier, a depletion type transistor (Q.sub.34) is used as a reference constant current source, which is independent of a power supply voltage (V.sub.DD), for the two values of the address signal of a TTL level.
Abstract: A semiconductor memory device wherein a redundancy memory cell array incorporated with main memory cell matrixes is disclosed. Memory cells of the main memory cell matrixes are selected by first and third decoders while memory cells of the redundancy memory cell array are selected by second and third decoders. When the redundancy memory cell array is selected by the second decoder, the transmission of a clock signal to the first decoders is stopped by a switching circuit.
Abstract: A semiconductor memory device comprising a plurality of memory blocks each including a sense amplifier array and a pair of memory cell groups disposed on both sides of the sense amplifier array, a row decoder for selecting a row line in the plurality of memory blocks, pairs of bus lines, each pair corresponding to one of the sense amplifier arrays and, a column decoder. The column decoder is provided commonly to the plurality of memory blocks and selectively connects a pair of input/output terminals of a sense amplifier of the sense amplifier array in each of the memory blocks to a corresponding one of the pairs of bus lines.
Abstract: A dynamic semiconductor memory device comprising a plurality of memory blocks each including a sense amplifier array and a pair of memory cell groups, a row decoder for selecting a row line within the plurality of memory blocks, a column decoder which is common to the plurality of memory blocks and which selectively connects a sense amplifier in each of the memory blocks to a corresponding one of the pairs of bus lines. The device also includes row block decoders which selectively enable the sense amplifier array of one of the memory blocks according to block selecting address signals, and block bus line decoders which selectively connect the pair of bus lines of each of the memory blocks to a pair of data buses according to the block selecting address signals.
Abstract: A semiconductor memory device having flip-flop circuits, in which first and second bit lines are connected to each of the flip-flop circuits as a sense amplifier, the potential of the second bit line being opposite to the potential of the first bit line, and the first and second data bus lines cross perpendicularly to the first and second bit lines, respectively, the first and second dummy lines are arranged in parallel with the first and second data bus lines respectively, in order to prevent erroneous operation of an I/O amplifier connected to the first and second data bus lines.
Abstract: An integrated semiconductor memory device is formed on a semiconductor substrate of one conductivity type on which there are provided peripheral circuits consisting of a pluality of memory cells each containing a storage capacitor and an IG FET. The IG FET in each memory cell acts as a transfer gate which is disposed on a surface region having the same conductivity type as that of the substrate and higher impurity concentrations than that of the substrate. The transfer gate has a gate threshold value which is higher than that of the IG FET in the peripheral circuits and which is insensitive to a noise pulse supplied thereto, whereby the destruction of data by noise pulse can be effectively prevented.