Abstract: A gate driver circuit includes one or more datastores configured to store one or more result registers, timer circuitry configured to generate a timing signal, and logic circuitry. The logic circuitry is configured to drive switching circuitry using a switching signal and determine a triggering point of a first cycle of the switching signal. In response to the determination of the triggering point, the logic circuitry is configured to control, using the switching signal, one or more analog-to-digital converters (ADCs) to store a first data sample at the one or more result registers. In response to a determination that the switching signal does not include a triggering point, the logic circuitry is configured to control, using the timing signal, the one or more ADCs to store a second data sample at the one or more result registers.

Abstract: A circuit includes one or more datastores configured to store a result register and a readout counter value and logic circuitry coupled to the one or more datastores. The logic circuitry is configured to cause, for a cycle of a plurality of cycles of a periodic signal, one or more analog-to-digital converters (ADCs) to store data to the result register and modify the readout counter value in response to the one or more ADCs storing the data to the result register for the cycle. In response to a read request for the data at the result register for the cycle, the logic circuitry is configured to output the data stored by the result register, output the readout counter value for the cycle, and, after the output of the readout counter value, set the readout counter value to a predetermined value.

Abstract: Circuits, devices and systems that include a low voltage test for common mode transient immunity (CMTI). The CMTI test of this disclosure may be used in a variety of applications, such as a data transmission circuit configured to communicate across galvanic isolation. A differential circuit may include two signal paths. For robust common mode transient rejection, the first signal path should be the same as the second signal path. Differences in the resistance, inductance, and capacitance between the two signal paths may result in common mode noise being measured as a differential signal at the output terminals. Devices according to the techniques of this disclosure are configured to enter a test mode to conduct a low voltage test that outputs a measurement of CMTI at any phase of production or field use.

Abstract: An example controller for a flyback power converter includes a secondary-side circuit comprising a secondary-side controller. The secondary-side controller is configured to sense an electrical characteristic of a secondary-side output of the flyback power converter, select, based on the sensed electrical characteristic, a power mode, and transmit, over a communication channel, a control message specifying the selected power mode. A primary-side circuit of the controller includes a primary-side controller. The primary-side controller is configured to receive, over the communication channel, the control message specifying the selected power mode and control primary-side flyback drive circuitry of the primary-side circuit to drive a primary-side output of the flyback power converter according to the selected power mode so as to control a value of the electrical characteristic of the secondary-side output of the flyback power converter.

Abstract: This disclosure is directed to circuits and techniques for protecting a power switch when the power switch is turned ON. A driver circuit may detect whether the power switch is in a desaturation mode or an overcurrent state based on a signal at a detection pin, and disable the power switch in response to detecting that the power switch is in the desaturation mode or the overcurrent state. In addition, the driver circuit may detect whether the power switch is trending towards a safe operating area (SOA) limit of the power switch based on a rate of change of the signal, and disable the power switch in response to detecting that the power switch is trending towards the SOA limit.

Abstract: This disclosure is directed to circuits and techniques for protecting a power switch when the power switch is turned ON. A driver circuit may detect whether the power switch is in a desaturation mode or an overcurrent state based on a signal at a detection pin, and disable the power switch in response to detecting that the power switch is in the desaturation mode or the overcurrent state. In addition, the driver circuit may detect whether the power switch is trending towards a safe operating area (SOA) limit of the power switch based on a rate of change of the signal, and disable the power switch in response to detecting that the power switch is trending towards the SOA limit.

Abstract: An example controller for a flyback power converter includes a secondary-side circuit comprising a secondary-side controller. The secondary-side controller is configured to sense an electrical characteristic of a secondary-side output of the flyback power converter, select, based on the sensed electrical characteristic, a power mode, and transmit, over a communication channel, a control message specifying the selected power mode. A primary-side circuit of the controller includes a primary-side controller. The primary-side controller is configured to receive, over the communication channel, the control message specifying the selected power mode and control primary-side flyback drive circuitry of the primary-side circuit to drive a primary-side output of the flyback power converter according to the selected power mode so as to control a value of the electrical characteristic of the secondary-side output of the flyback power converter.

Abstract: This disclosure is directed to circuits and techniques for protecting a body diode of a power switch from an inductive load when the power switch is turned OFF. A driver circuit may detect whether the power switch is in a desaturation mode when the power switch is turned ON and disable the power switch in response to detecting that the power switch is in the desaturation mode. In addition, the driver circuit may detect whether the body diode of the power switch needs protection when the power switch is turned OFF, and in response to detecting that the body diode needs protection, control the power switch according to a body diode protection scheme.

Abstract: A method of protecting a gate driver circuit includes receiving an input signal to energize a gate driver output of the gate driver circuit, determining that an abnormal operating condition exists at the gate driver output, continuously energizing the gate driver output for a time period, and entering a pulsed mode of operation for energizing the gate driver output after the time period has lapsed.

Abstract: Devices are provided in which a metastable state can be detected in a memory device by means of a metastability detector. Corresponding information can be conveyed to a further device which, in dependence thereon, can process data from the memory device.

Abstract: A method of protecting a gate driver circuit includes receiving an input signal to energize a gate driver output of the gate driver circuit, determining that an abnormal operating condition exists at the gate driver output, continuously energizing the gate driver output for a time period, and entering a pulsed mode of operation for energizing the gate driver output after the time period has lapsed.

Abstract: A gate driver is described that includes a gate signal module configured to output a gate signal of the gate driver for driving a gate terminal of a semiconductor device. The gate driver further includes a test module configured to generate a simulated failure condition at a semiconductor device during a test of a monitoring and protection feature of the gate driver. The gate drier further includes a monitor module configured to output an indication of the simulated failure condition in response to detecting the simulated failure condition at the semiconductor device.

Abstract: Devices are provided in which a metastable state can be detected in a memory device by means of a metastability detector. Corresponding information can be conveyed to a further device which, in dependence thereon, can process data from the memory device.

Abstract: An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.

Abstract: A gate driver is described that includes a gate signal module configured to output a gate signal of the gate driver for driving a gate terminal of a semiconductor device. The gate driver further includes a test module configured to generate a simulated failure condition at a semiconductor device during a test of a monitoring and protection feature of the gate driver. The gate drier further includes a monitor module configured to output an indication of the simulated failure condition in response to detecting the simulated failure condition at the semiconductor device.

Abstract: In accordance with an aspect of the invention, there is provided an SPI interface including a plurality of synchronizers configured to receive a plurality of SPI signals and an internal clock signal and synchronize the received SPI signals using the internal clock signal. The SPI interface also includes an SPI protocol handler configured to receive the synchronized SPI signals and the internal clock signal, and detect and evaluate signal transitions of at least one of the synchronized SPI signals according to an SPI protocol.

Abstract: A circuit arrangement is provided, including a storage circuit and an output circuit. The storage circuit is configured to provide a first output signal and a second output signal. The output circuit is configured to receive the first output signal and the second output signal and configured to provide an output signal having one of a first signal level and a second signal level, and to only switch from the first signal level to the second signal level if the difference between the first output signal and the second output signal exceeds a threshold. The circuit arrangement is configured to hold the first output signal and the second output signal independent of a difference between the first output signal and the second output signal after the switching has been carried out.

Abstract: An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.

Abstract: A circuit arrangement is provided, including a storage circuit and an output circuit. The storage circuit is configured to provide a first output signal and a second output signal. The output circuit is configured to receive the first output signal and the second output signal and configured to provide an output signal having one of a first signal level and a second signal level, and to only switch from the first signal level to the second signal level if the difference between the first output signal and the second output signal exceeds a threshold. The circuit arrangement is configured to hold the first output signal and the second output signal independent of a difference between the first output signal and the second output signal after the switching has been carried out.

Abstract: An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.