Abstract: An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.

Abstract: Method for the memory self-test of embedded memories (2, 3, 4) in semiconductor chips (1), a memory address range (8) being assigned to a memory (2) to be tested and addresses from the same memory address range of the memory to be tested being allocated to at least one memory self-test controller register (6R2) of a memory self-test controller for storing memory test configuration data.

Abstract: Method for the memory self-test of embedded memories (2, 3, 4) in semiconductor chips (1), a memory address range (8) being assigned to a memory (2) to be tested and addresses from the same memory address range of the memory to be tested being allocated to at least one memory self-test controller register (6R2) of a memory self-test controller for storing memory test configuration data.

Abstract: A semiconductor device is disclosed that has a plurality of I/O pins that are configurable to selectively output three sets of signals selected from the group consisting of (i) a read enable signal and a write enable signal, (ii) a combined read and write enable signal, (iii) a read enable signal and a pair of byte write enable signals, and (iv) a row address strobe signal, and a column address strobe signal.

Abstract: A semiconductor device is disclosed that has a plurality of I/O pins that are configurable to selectively output three sets of signals selected from the group consisting of (i) a read enable signal and a write enable signal, (ii) a combined read and write enable signal, (iii) a read enable signal and a pair of byte write enable signals, and (iv) a row address strobe signal, and a column address strobe signal.

Abstract: A circuit and a method for setting a digital potential at an integrated circuit output pin in which pull up/pull down circuitry holds a defined value at the output pin during the power down of the integrated circuit. A primary driver responsive to a state of the integrated circuit sets the output pin while the integrated circuit is in an active mode of operation, and secondary driver sets the output pin while the integrated circuit is in an inactive mode of operation. Control logic is provided as being responsive to a change in the mode of operation of the integrated circuit from its active mode to its inactive mode for generating a control signal relative to the state of the integrated circuit.

Abstract: A circuit and a method for setting a digital potential at an integrated circuit output pin in which pull up/pull down circuitry holds a defined value at the output pin during the power down of the integrated circuit. A primary driver responsive to a state of the integrated circuit sets the output pin while the integrated circuit is in an active mode of operation, and secondary driver sets the output pin while the integrated circuit is in an inactive mode of operation. Control logic is provided as being responsive to a change in the mode of operation of the integrated circuit from its active mode to its inactive mode for generating a control signal relative to the state of the integrated circuit.

Abstract: A clock generator supplying clock signals to a synchronous system is disabled in response to a first synchronous signal from the synchronous system and enabled in response to an asynchronous signal. Upon the enabling of the clock generator in response to the synchronous signal, a second synchronous signal is transmitted to the synchronous system to notify the system that the clock generator is enabled. In the preferred embodiment, the register bits in a shift register are set by the first synchronous signal to a value that disables the clock generator and then the register bits can be set by an asynchronous signal to a value that enables, or wakes up, the clock generator. The first synchronous signal that is used to disable the clock generator is also used to initiate a synchronous counter that counts a pre-established number of clock signals from the clock generator and then transmits a synchronous wake-up signal to the synchronous system.

Abstract: A semiconductor device is disclosed that has a plurality of I/O pins that are configurable to selectively output three sets of signals selected from the group consisting of (i) a read enable signal and a write enable signal, (ii) a combined read and write enable signal, (iii) a read enable signal and a pair of byte write enable signals, and (iv) a row address strobe signal, and a column address strobe signal.

Abstract: An access control system (10) for controlling access to a shared resource among a plurality of service requestors is described. When a service requestor seeks access to the shared resource, it generates a service request signal which includes its assigned unique service request priority number. The outputs of all the service requesters are applied to pipelined first and second OR-trees (75, 78) which produce an OR-ed output signal. The OR-ed output signal is then applied to an access control unit (38) which performs an arbitration protocol to determine the highest priority number. Each service requester includes a state machine which selectively applies the bits of its priority number to the OR-trees (75, 78). The use of pipelined protocol with two OR-trees (75, 78) reduces cycle consumption and permits arbitration within a single clock cycle.

Abstract: A method and system for accurately indicating test results from testing routines of a self-check operation during initialization or reset of the system utilize test result bits in a secure status register that must be sequentially reset to indicate a successful completion of the self-check operation. The system is a microcontroller that can be incorporated into various consumer products requiring digital processing. Each test result bit represents a distinct component of the system that is tested during the self-check operation. The test result bits in the status register can only be reset one at a time, by activating a demultiplexer which resets a particular test result bit in response to a successful testing of a component. However, the demultiplexer can only be activated by modifying a control bit in an access register that is protected by a double password scheme. To modify the control bit, the CPU must provide two valid passwords.

Abstract: The invention relates to a method and an arrangement for operating a bus system having at least one master unit and at least one slave unit, having a bus and a bus control unit for the bus arbitration and for controlling the data transfer. The data transmission is split into a request data transfer and a response data transfer, and, in the time between the request data transfer and the response data transfer, the bus is cleared for the data transmissions of other master units in a first data transmission configuration, or the bus is blocked between the request data transfer and the response data transfer, in a second data transmission configuration and slave units. In the case of a response transfer, the master and slave are changed round.

Abstract: A circuit configuration for generating a reset signal includes a bistable switch element assuming a preferential state upon application of a supply voltage. The bistable switch element has an output carrying a reset signal in the preferential state and has an input. An on and off switchable reference voltage source has a control input connected to the output of the bistable switch element. The on and off switchable reference voltage source is switched on in the preferential state of the bistable switch element. An on and off switchable delay line has a control terminal connected to the output of the bistable switch element, an output connected to the input of the bistable switch element, and a reference input connected to the on and off switchable reference voltage source for switching on the delay line in the preferential state of the bistable switch element.