Patents by Inventor Tommaso Zerilli
Tommaso Zerilli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11868488Abstract: An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.Type: GrantFiled: November 28, 2022Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Carmelo Condemi, Francesco Tomaiuolo, Tommaso Zerilli
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Patent number: 11722323Abstract: Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.Type: GrantFiled: August 25, 2022Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Tommaso Zerilli, Carmelo Condemi, Francesco Tomaiuolo
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Patent number: 11657877Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.Type: GrantFiled: July 2, 2021Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Francesco Tomaiuolo, Carmelo Condemi, Tommaso Zerilli
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Publication number: 20230086754Abstract: An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.Type: ApplicationFiled: November 28, 2022Publication date: March 23, 2023Inventors: Antonino Mondello, Carmelo Condemi, Francesco Tomaiuolo, Tommaso Zerilli
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Patent number: 11514174Abstract: An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.Type: GrantFiled: January 23, 2019Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Carmelo Condemi, Francesco Tomaiuolo, Tommaso Zerilli
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Patent number: 11469909Abstract: Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.Type: GrantFiled: December 28, 2018Date of Patent: October 11, 2022Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Tommaso Zerilli, Carmelo Condemi, Francesco Tomaiuolo
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Publication number: 20210335425Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.Type: ApplicationFiled: July 2, 2021Publication date: October 28, 2021Inventors: Antonino Mondello, Francesco Tomaiuolo, Carmelo Condemi, Tommaso Zerilli
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Patent number: 11056192Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.Type: GrantFiled: December 21, 2018Date of Patent: July 6, 2021Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Francesco Tomaiuolo, Carmelo Condemi, Tommaso Zerilli
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Publication number: 20200233967Abstract: An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.Type: ApplicationFiled: January 23, 2019Publication date: July 23, 2020Inventors: Antonino Mondello, Carmelo Condemi, Francesco Tomaiuolo, Tommaso Zerilli
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Publication number: 20200213138Abstract: Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Antonino Mondello, Tommaso Zerilli, Carmelo Condemi, Francesco Tomaiuolo
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Publication number: 20200202944Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.Type: ApplicationFiled: December 21, 2018Publication date: June 25, 2020Inventors: Antonino Mondello, Francesco Tomaiuolo, Carmelo Condemi, Tommaso Zerilli
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Patent number: 9262317Abstract: Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device.Type: GrantFiled: January 6, 2014Date of Patent: February 16, 2016Assignee: Micron Technology, Inc.Inventors: Paolo Rolandi, Sandra Lospalluti, Raffaele Bufano, Stefano Andreoli, Tommaso Zerilli
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Patent number: 9251065Abstract: Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.Type: GrantFiled: February 9, 2015Date of Patent: February 2, 2016Assignee: Micro Technology, Inc.Inventors: Paolo Rolandi, Sandra Lospalluti, Raffaele Bufano, Stefano Andreoli, Tommaso Zerilli
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Publication number: 20150220431Abstract: Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.Type: ApplicationFiled: February 9, 2015Publication date: August 6, 2015Inventors: Paolo Rolandi, Sandra Lospalluti, Raffaele Bufano, Stefano Andreoli, Tommaso Zerilli
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Patent number: 8954660Abstract: Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.Type: GrantFiled: January 7, 2014Date of Patent: February 10, 2015Assignee: Micron Technology, Inc.Inventors: Paolo Rolandi, Sandra Lospalluti, Raffaele Bufano, Stefano Andreoli, Tommaso Zerilli
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Publication number: 20140195723Abstract: Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device.Type: ApplicationFiled: January 6, 2014Publication date: July 10, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Paolo Rolandi, Sandra Lospalluti, Raffaele Bufano, Stefano Andreoli, Tommaso Zerilli
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Publication number: 20140189220Abstract: Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.Type: ApplicationFiled: January 7, 2014Publication date: July 3, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Paolo Rolandi, Sandra Lospalluti, Raffaele Bufano, Stefano Andreoli, Tommaso Zerilli
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Patent number: 8635398Abstract: Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.Type: GrantFiled: December 30, 2008Date of Patent: January 21, 2014Assignee: Micron Technology, Inc.Inventors: Paolo Rolandi, Sandra Lospalluti, Raffaele Bufano, Stefano Andreoli, Tommaso Zerilli
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Patent number: 8626990Abstract: Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device.Type: GrantFiled: December 30, 2008Date of Patent: January 7, 2014Assignee: Micron Technology, Inc.Inventors: Paolo Rolandi, Sandra Lospalluti, Raffaele Bufano, Stefano Andreoli, Tommaso Zerilli
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Patent number: 8607028Abstract: A method and a memory device are provided for accessing a storage location. The method includes storing an extended address value in a register in a non-volatile memory device. The method further includes subsequently receiving multiple addresses and combining the stored extended address value with each of the multiple received addresses to produce multiple combined addresses. The method further includes accessing multiple storage locations within the non-volatile memory device based, at least in part, on the multiple combined addresses.Type: GrantFiled: December 30, 2008Date of Patent: December 10, 2013Assignee: Micron Technology, Inc.Inventors: Poorna Kale, Chris Bueb, Tommaso Zerilli, Raffaele Bufano, Sandra Lospalluti, Marco Gibilaro