Abstract: Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.

Abstract: Example embodiments for providing enhanced addressability for a serial non-volatile memory device may comprise accessing a storage location based, at least in part, on an extended address value and an address, the extended address value to identify a subset of storage locations from a plurality of storage locations, the address to identify the storage location within the subset of storage locations.

Abstract: A generator circuit for voltage ramps is provided that includes a differential stage with positive feedback coupled between a first and a second voltage reference and having a first output connected to a control terminal of a first output transistor. The first output transistor is connected at an output terminal of the ramp generator circuit to a capacitive charge to be biased with voltage ramps. The ramp generator circuit also includes a second output transistor parallel connected to the first output transistor and having the control terminal connected to a second output of the differential stage.

Abstract: A generator circuit for voltage ramps is provided that includes a differential stage with positive feedback coupled between a first and a second voltage reference and having a first output connected to a control terminal of a first output transistor. The first output transistor is connected at an output terminal of the ramp generator circuit to a capacitive charge to be biased with voltage ramps. The ramp generator circuit also includes a second output transistor parallel connected to the first output transistor and having the control terminal connected to a second output of the differential stage.

Abstract: A bias circuit for read amplifier circuits for memories includes at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors includes a P-channel diode connected transistor and an N-channel transistor connected in series, with an enable transistor interposed therebetween. The first circuit branch drives a capacitive load for coupling to the supply voltage. The bias circuit further includes reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch for charging the capacitive load. A circuit portion, which controls the charging current of the capacitive load, includes a feedback loop between the reference current amplifier circuit branches and the capacitive load.

Abstract: A boosted voltage driving circuit includes an inverter circuit with positive feedback and a selective breaking circuit. The selective breaking circuit disconnects the positive feedback from the output load during an operation phase of the boosted voltage driving circuit in order to reduce energy consumption. In a preferred embodiment, the boosted voltage driving circuit is the final stage of a decoder circuit for selecting and deselecting a line or column of a memory array, and the positive feedback is disconnected during a deselection phase in which the line or column is deselected. The present invention also provides a boosted voltage driving circuit that includes first, second, and third transistors and a selective breaking circuit. The first transistor is connected between a supply voltage and an output node, the second transistor is connected between the output node and ground, and the third transistor is connected between the supply voltage and the gate of the first transistor.