Patents by Inventor Tommy K. Eng

Tommy K. Eng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6971073
    Abstract: An electronic design automation system provides optimization of RTL models of electronic designs, to produce detailed constraints and data precisely defining the requirements for the back-end flows leading to design fabrication. The system takes a RTL model of an electronic design and maps it into an efficient, high level hierarchical representation of the hardware implementation of the design. Automatic partitioning partitions the hardware representation into functional partitions, and creates a fully characterized performance envelope for a range of feasible implementations for each of the partitions, using accurate placement based wire load models. Chip-level optimization selects and refines physical implementations of the partitions to produce compacted, globally routed floorplans. Chip-level optimization iteratively invokes re-partitioning passes to refine the partitions and to recompute the feasible implementations.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: November 29, 2005
    Assignee: Tera Systems, Inc.
    Inventor: Tommy K. Eng
  • Publication number: 20020059553
    Abstract: An electronic design automation system provides optimization of RTL models of electronic designs, to produce detailed constraints and data precisely defining the requirements for the back-end flows leading to design fabrication. The system takes a RTL model of an electronic design and maps it into an efficient, high level hierarchical representation of the hardware implementation of the design. Automatic partitioning partitions the hardware representation into functional partitions, and creates a fully characterized performance envelope for a range of feasible implementations for each of the partitions, using accurate placement based wire load models. Chip-level optimization selects and refines physical implementations of the partitions to produce compacted, globally routed floorplans. Chip-level optimization iteratively invokes re-partitioning passes to refine the partitions and to recompute the feasible implementations.
    Type: Application
    Filed: December 28, 2001
    Publication date: May 16, 2002
    Inventor: Tommy K. Eng
  • Patent number: 6360356
    Abstract: An electronic design automation system provides optimization of RTL models of electronic designs, to produce detailed constraints and data precisely defining the requirements for the back-end flows leading to design fabrication. The system takes a RTL model of an electronic design and maps it into an efficient, high level hierarchical representation of the hardware implementation of the design. Automatic partitioning partitions the hardware representation into functional partitions, and creates a fully characterized performance envelope for a range of feasible implementations for each of the partitions, using accurate placement based wire load models. Chip-level optimization selects and refines physical implementations of the partitions to produce compacted, globally routed floorplans. Chip-level optimization iteratively invokes re-partitioning passes to refine the partitions and to recompute the feasible implementations.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: March 19, 2002
    Assignee: Tera Systems, Inc.
    Inventor: Tommy K. Eng
  • Patent number: 6145117
    Abstract: An electronic design automation system provides optimization of RTL models of electronic designs, to produce detailed constraints and data precisely defining the requirements for the back-end flows leading to design fabrication. The system takes an RTL model of an electronic design and maps it into an efficient, high level hierarchical representation of the hardware implementation of the design. Automatic partitioning partitions the hardware representation into functional partitions, and creates a fully characterized performance envelope for a range of feasible implementations for each of the partitions, using accurate placement based wire load models. Chip-level optimization selects and refines physical implementations of the partitions to produce compacted, globally routed floorplans. Chip-level optimization iteratively invokes re-partitioning passes to refine the partitions and to recompute the feasible implementations.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: November 7, 2000
    Assignee: Tera Systems Incorporated
    Inventor: Tommy K. Eng
  • Patent number: 5638092
    Abstract: A cursor control system and method for moving a cursor on a computer screen in response to movement of a ring over a keyboard. A ring contains a transmitter circuit which is activated by a switch positioned on the ring. A signal generated by the transmitter circuit is transmitted to a receiver attached to a computer keyboard. The receiver detects motion of the transmitter circuit over the keyboard and, in response, generates signals which are used to control the movement of the cursor on the computer screen.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: June 10, 1997
    Inventors: Tommy K. Eng, Harold G. Alles