Abstract: Systems and methods for digital signal synthesis with variable sample rate digital-to-analog converters (DACs) in accordance with various embodiments of the invention are described. One embodiment includes a digital frequency generator that includes a direct digital frequency synthesizer (DDFS); a digital-to-analog converter (DAC); a frequency/phase estimation circuit; a stable reference clock (REF CLK); a variable frequency sample clock; a frequency control word (FCW); where the DAC is sampled by the variable frequency sample clock; where the DDFS is clocked by the variable frequency sample clock; where the frequency/phase estimation circuit receives as inputs the stable REF CLK and the variable frequency sample clock and estimates a FCW frequency error and adjusts the FCW to the DDFS; where the DDFS receives the FCW and outputs a digital sine codeword at the variable frequency sample clock to the DAC, where the FCW to the DDFS is continuously adjusted to track the variable frequency sample clock.

Abstract: Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.

Abstract: Systems and methods for digitally synthesizing chirp signal in a low intermediate frequency (IF) band and using frequency multipliers to generate a higher frequency signal for radar applications are described. An embodiment includes a chirp signal generator that includes: a direct digital frequency synthesizer (DDFS) that is configured to receive an input sync signal and a frequency reference signal and generate several chirp signals at a first frequency that is in a low intermediate frequency (IF) band, several frequency multipliers that are configured to increase the chirp signals to higher frequencies and several bandpass filter circuits that are configured to remove nonlinearities from the chirp signals to generate a clean output signal.

Abstract: Systems and methods for synthesis of a modulated RF signal using a variety of modulation schemes are described. An embodiment includes a direct frequency synthesizer with frequency modulated continuous wave (FMCW) modulation that includes: a high speed BAW resonator that generates a frequency signal; a BAW oscillator that receives the frequency signal and generates an output BAW clock signal (BAW CLK); a frequency and phase estimation circuit that receives a reference clock signal from a reference clock (REF CLK) and the BAW CLK and generates a frequency error and a phase error; a frequency chirp generator that receives chirp parameters, a chirp sync signal and generates a nominal frequency control word (FCW); and a high speed digital to analog converter (HS DAC) that receives the BAW CLK and the codeword and outputs an analog signal.

Abstract: Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.

Abstract: Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.

Abstract: Systems and methods for synthesis of a modulated RF signal using a variety of modulation schemes are described. An embodiment includes a direct frequency synthesizer with frequency modulated continuous wave (FMCW) modulation that includes: a high speed BAW resonator that generates a frequency signal; a BAW oscillator that receives the frequency signal and generates an output BAW clock signal (BAW CLK); a frequency and phase estimation circuit that receives a reference clock signal from a reference clock (REF CLK) and the BAW CLK and generates a frequency error and a phase error; a frequency chirp generator that receives chirp parameters, a chirp sync signal and generates a nominal frequency control word (FCW); and a high speed digital to analog converter (HS DAC) that receives the BAW CLK and the codeword and outputs an analog signal.

Abstract: Systems and methods for digitally synthesizing chirp signal in a low intermediate frequency (IF) band and using frequency multipliers to generate a higher frequency signal for radar applications are described. An embodiment includes a chirp signal generator that includes: a direct digital frequency synthesizer (DDFS) that is configured to receive an input sync signal and a frequency reference signal and generate several chirp signals at a first frequency that is in a low intermediate frequency (IF) band, several frequency multipliers that are configured to increase the chirp signals to higher frequencies and several bandpass filter circuits that are configured to remove nonlinearities from the chirp signals to generate a clean output signal.

Abstract: The present embodiments introduce an approach for designing perfectly linear DACs using non-ideal components. The approach may eliminate the non-linearity of the DAC and remove the conventional trade-offs between performance and complexity.

Abstract: The present embodiments introduce an approach for designing perfectly linear DACs using non-ideal components. The approach may eliminate the non-linearity of the DAC and remove the conventional trade-offs between performance and complexity.

Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

Abstract: Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.

Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

Abstract: A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.

Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

Abstract: Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

Abstract: A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.

Abstract: A dielectric resonator oscillator includes a dielectric resonator; a transmission line disposed adjacent the dielectric resonator; an active device having an input electrically connected to the transmission line; a matching network having an input electrically connected to an output of the active device and an output configured to be connected to a load; wherein both the transmission line and the active device are positioned sufficiently close to the dielectric resonator to form part of a resonant circuit with the dielectric resonator.

Abstract: A parallel delta sigma modulator architecture is disclosed. The parallel delta sigma modulator architecture includes a signal demultiplexer configured to receive an input signal and to demultiplex the input signal to output a plurality of streams, a plurality of delta sigma modulators executing in parallel, each delta sigma modulator configured to receive a stream from the plurality of streams and to generate a delta sigma modulated output, and a signal multiplexer configured to receive a plurality of delta sigma modulated outputs from the plurality of delta sigma modulators and to multiplex together the plurality of delta sigma modulated outputs into a pulse train.