Abstract: Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.

Abstract: Provided is a method to process a pulse width coded signal. The method includes digitizing a received pulse width coded signal and transforming the digitized signal to at least one of power domain and absolute value domain. The converting produces a converted signal. The method also includes estimating a signal power of the converted signal in a wide band filter to produce data representative of a first signal having first type signal shape properties and estimating a signal power of the converted signal in a narrow band filter to produce data representative of a second signal having second type signal shape properties. Finally, the first and second type data are compared to produce information representative of pulse width characteristics of the received signal.

Abstract: Sample rate reduction in data communication receivers. Digital sampling of analog data is performed using a reduced sample rate. The reduction factor may be any number of factors including a factor that divides the sample rate by a factor of two. The reduction of the sampling frequency is from a sampling frequency that is greater than twice the highest frequency component in an analog input signal. These analog input signals may be I and Q streams in certain embodiments. A digital interpolation filter may be employed to increase (up-convert) the sample rate of a digital signal before it is input to a VID filter that is used to recover the transmitted symbols from the over-sampled data stream. In this embodiment, this technique allows a front end of a communication receiver to be clocked at a lower sampling rate without affecting the performance of the VID filter.

Abstract: A frequency translation module for a broadband multi-channel communication system may include an analog signal converter, a digital channel selection device, and a digital-to-analog (D/A) converter. The analog signal converter is configured to receive a plurality of analog signals, to select analog signals residing in a predefined frequency band, and to convert each of the selected analog signals into a digital signal. The digital channel selection device is configured to process digital signals corresponding to the selected analog signals and to generate a composite output of digital signals representative of the selected analog signals. The D/A converter is configured to translate the composite output to an analog signal output decodable by a receiver. Further, the frequency translation module may include a mixer configured to upconvert the analog signal output to a frequency decodable by the receiver.

Abstract: In an embodiment, a receiver for processing a RF input signal having a variable signal strength includes an RF amplifier, an IF amplifier, and a controller. The RF amplifier is configured to receive and amplify the RF input signal. The IF amplifier is coupled to an output of the RF amplifier. The controller controls gains of the RF amplifier and the IF amplifier during times of falling signal strength. A gain of the IF amplifier is increased as the signal strength falls until a first amplitude threshold is reached for the falling signal strength. If the signal strength falls beyond the first threshold, a gain of the RF amplifier is increased until a second amplitude threshold is reached. The second amplitude threshold is lower than the first amplitude threshold. If the signal strength falls below the second amplitude threshold, the gain of the IF amplifier is further increased.

Abstract: Provided is a method to process a pulse width coded signal. The method includes digitizing a received pulse width coded signal and transforming the digitized signal to at least one of power domain and absolute value domain. The converting produces a converted signal. The method also includes estimating a signal power of the converted signal in a wide band filter to produce data representative of a first signal having first type signal shape properties and estimating a signal power of the converted signal in a narrow band filter to produce data representative of a second signal having second type signal shape properties. Finally, the first and second type data are compared to produce information representative of pulse width characteristics of the received signal.

Abstract: Certain aspects of a method and system for satellite communication are disclosed. Aspects of one method may include a receiver that handles digital video broadcasting. The receiver may be enabled to dynamically vary spacing between one or more pilots within at least one frame based on a determined symbol rate. The size of each of a plurality of received programs may be determined and the spacing between one or more pilots may be dynamically varied based on the determined size of each of the plurality of received programs.

Abstract: Provided is a method to process a pulse width coded signal. the method includes digitizing a received pulse width coded signal and transforming the digitized signal to at least one of power domain and absolute value domain. The converting produces a converted signal. The method also includes estimating a signal power of the converted signal in a wide band filter to produce data representative of a first signal having first type signal shape properties and estimating a signal power of the converted signal in a narrow band filter to produce data representative of a second signal having second type signal shape properties. Finally, the first and second type data are compared to produce information representative of pulse width characteristics of the received signal.

Abstract: The present invention includes a method of determining a phase estimate for an input signal having pilot symbols. The method includes receiving a plurality of pilot symbols, and then multiplying two or more pilot symbol slots by corresponding correlator coefficients to correct a phase estimate of the input signal.

Abstract: A method and apparatus for the detection and correction of large carrier offsets. A set of known correction carrier offsets are used to translate an input signal having a carrier offset. After applying each correction carrier offset, a state of a timing recovery loop is evaluated. The set of known correction carrier offsets are sequentially used to translate the input signal until the timing recovery loop is locked. The carrier offset is substantially acquired when the timing recovery loop is locked.

Abstract: A method and apparatus is disclosed for detecting the amount of unknown offset present in a received data stream. The unknown phase offset may offset the phase of the transmitted data stream from the received data stream. A phase detector uses a soft-decision slicer to estimate the content of a modulation transmitted data stream. The soft-decision slicer generates an estimate of the transmitted data stream depending on the location of the received data stream in relation to a transfer function of the soft-decision slicer depending on the modulation scheme of the received data stream. The phase detector uses the estimate of the transmitted data stream to calculate the amount of the unknown phase offset.

Abstract: An update algorithm for equalizer coefficients in a communications system using phase correction symbols. Instead of using a traditional all symbols slicer update algorithm, the equalizer is updated during phase correction symbols for optimal performance in low signal-to-noise ratio conditions. In lower signal-to-noise ratio conditions, the equalizer uses a phase correction circuit to compensate for distortion caused by a communication channel when a demodulated data stream contains an unknown phase offsets resulting from a fast dynamic distortion. More specifically, the phase correction circuit uses a phase correction signal to correct for the unknown phase offsets in a demodulated data stream in lower signal-to-noise ratio conditions. The equalizer then corrects for distortion caused by the communication channel based upon the phase corrected demodulated data stream.

Abstract: Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.

Abstract: Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.

Abstract: In an integrated satellite receiver, improved header acquisition techniques are described for quickly locating a header symbol sequence in a data stream substantially implemented on a single CMOS integrated circuit. To identify the location of a header symbol sequence in a data stream, a selected header acquisition technique employs a real time correlator followed by an accumulator. In accordance with an alternative embodiment which reduces the cost very efficiently, a real time correlator is followed by a comparator to pick out and store the top N correlator values from NS symbols in a frame. The timing addresses associated with the stored correlator values are used during an accumulation mode of operation whereby a cumulative memory is used to accumulate the correlator value of each stored timing address. Once accumulation over a predetermined number of frames is finished, the largest or maximum value among the accumulated correlator values is identified.

Abstract: Provided is a method to process a pulse width coded signal. the method includes digitizing a received pulse width coded signal and transforming the digitized signal to at least one of power domain and absolute value domain. The converting produces a converted signal. The method also includes estimating a signal power of the converted signal in a wide band filter to produce data representative of a first signal having first type signal shape properties and estimating a signal power of the converted signal in a narrow band filter to produce data representative of a second signal having second type signal shape properties. Finally, the first and second type data are compared to produce information representative of pulse width characteristics of the received signal.

Abstract: An integrated burst FSK receiver is provided to receive and interpret an RF signal using FSK modulation. The integrated burst FSK receiver uses a programmable RF local oscillator to mix a received signal down to an IF range or baseband, where it is filtered and sampled for subsequent digital processing. Digital filtering and detection are employed to improve overall bit error rate performance and receiver sensitivity. A programmable digital low-pass or band-pass filter can also be used to suppress interference. A matched filter correlator can be used for detection and symbol timing adjustment in one mode, while an adaptive frequency comparator can be used in another mode. Circuits are provided that estimate carrier offset, frequency deviation and signal strength. These measurements can then be used to optimize the receiver performance. A method for receiving and interpreting an RF signal using FSK modulation is also provided.

Abstract: Sample rate reduction in data communication receivers. Digital sampling of analog data is performed using a reduced sample rate. The reduction factor may be any number of factors including a factor that divides the sample rate by a factor of two. The reduction of the sampling frequency is from a sampling frequency that is greater than twice the highest frequency component in an analog input signal. These analog input signals may be I and Q streams in certain embodiments. A digital interpolation filter may be employed to increase (up-convert) the sample rate of a digital signal before it is input to a VID filter that is used to recover the transmitted symbols from the over-sampled data stream. In this embodiment, this technique allows a front end of a communication receiver to be clocked at a lower sampling rate without affecting the performance of the VID filter.

Abstract: Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.

Abstract: A method for upgrading qualities of DRAM capacitors and wafer-to-wafer uniformity is disclosed. In order to effectively prevent wafers from contaminations, the invention uses an additional silane purge process in situ before performing a SHSG seeding process on the wafers. The silane purge process of this invention utilizes the original silane seeding gas inlet. In this manner, not only thicknesses and surface areas of the SHSG seeds and capacitances of DRAMs can be increased, but also wafer-to-wafer uniformity can be upgraded.