Patents by Inventor Tomoaki Atsumi
Tomoaki Atsumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8791461Abstract: In a semiconductor device including a digital circuit portion and an analog circuit portion having a capacitor portion provided over a substrate, the capacitor portion is provided with a first wiring, a second wiring and a plurality of blocks each having a plurality of capacitor elements. Further, each the plurality of capacitor elements provided in each block has a semiconductor film having a first impurity region and a plurality of second impurity regions provided apart with the first impurity region interposed therebetween, and a conductive film provided over the first impurity region with an insulating film therebetween. A capacitor is formed from the first impurity region, the insulating film, and the conductive film.Type: GrantFiled: September 26, 2013Date of Patent: July 29, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki Atsumi, Hiroki Inoue
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Publication number: 20140120858Abstract: An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p?1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.Type: ApplicationFiled: January 6, 2014Publication date: May 1, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masafumi ITO, Tomoaki Atsumi
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Publication number: 20140121787Abstract: Provided is a structure which is capable of central control of an electric device and a sensor device and a structure which can reduce power consumption of an electric device and a sensor device. A central control system includes at least a central control device, an output unit, and an electric device or a sensor device. The central control device performs arithmetic processing on information transmitted from the electric device or the sensor device and makes the output unit output information obtained by the arithmetic processing. It is possible to know the state of the electric device or the sensor device even apart from the electric device or the sensor device. The electric device or the sensor device includes a transistor which includes an activation layer using a semiconductor with the band gap wider than that of single crystal silicon.Type: ApplicationFiled: October 24, 2013Publication date: May 1, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Tatsuji Nishijima, Hidetomo Kobayashi, Tomoaki Atsumi, Kiyoshi Kato
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Patent number: 8712481Abstract: To provide for a movable electronic device a power receiving device that when charging a battery, simplifies charging of the battery from a power feeder, which is a power supply means, and does not have faults due to an external factor relating to a relay terminal, or damage of the relay terminal, that are caused by directly connecting the battery and the power feeder, and further, to provide an electronic device including the power receiving device. An antenna circuit and a booster antenna for supplying electric power are provided in a movable electronic device. The antenna circuit receives a radio signal such as an electromagnetic wave via the booster antenna, and electric power that is obtained through the receiving of the radio signal is supplied to the battery through a signal processing circuit.Type: GrantFiled: July 22, 2010Date of Patent: April 29, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka Shionoiri, Jun Koyama, Yoshiyuki Kurokawa, Shunpei Yamazaki, Takayuki Ikeda, Takeshi Osada, Tomoaki Atsumi, Masato Ishii
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Publication number: 20140108836Abstract: A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.Type: ApplicationFiled: October 16, 2013Publication date: April 17, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tatsuji Nishijima, Hidetomo Kobayashi, Tomoaki Atsumi, Kiyoshi Kato, Shunpei Yamazaki
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Patent number: 8692653Abstract: Objects of the invention are to provide a semiconductor device including an RFID, which can transmit and receive individual information without a check of remaining capacity of the battery and a change of the battery in accordance with deterioration over time of the battery for a driving power supply; and which maintains a favorable communication state even when electric power, as a power supply for driving, from an external radio wave or electromagnetic wave (carrier wave) is not sufficient. A battery is provided as a power supply for supplying electric power in the RFID, and electric power obtained by a power generation element is charged in the battery.Type: GrantFiled: March 12, 2007Date of Patent: April 8, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka Shionoiri, Konami Izumi, Jun Koyama, Yoshiyuki Kurokawa, Shunpei Yamazaki, Tomoaki Atsumi, Takeshi Osada, Takayuki Ikeda, Masato Ishii
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Publication number: 20140068300Abstract: To provide a microcontroller that can operate in a low power consumption mode. The microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register of the peripheral circuit is formed at an interface with a bus line. A power gate is provided for control of power supply, and the microcontroller can operate in the low power consumption mode where some circuits alone are active, in addition to in a normal operation mode where all circuits are active. A register with no power supply in the low power consumption mode, such as a register of the CPU, includes a volatile memory and a nonvolatile memory.Type: ApplicationFiled: August 29, 2013Publication date: March 6, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tatsuji Nishijima, Hidetomo Kobayashi, Tomoaki Atsumi, Kiyoshi Kato
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Publication number: 20140027882Abstract: In a semiconductor device including a digital circuit portion and an analog circuit portion having a capacitor portion provided over a substrate, the capacitor portion is provided with a first wiring, a second wiring and a plurality of blocks each having a plurality of capacitor elements. Further, each the plurality of capacitor elements provided in each block has a semiconductor film having a first impurity region and a plurality of second impurity regions provided apart with the first impurity region interposed therebetween, and a conductive film provided over the first impurity region with an insulating film therebetween. A capacitor is formed from the first impurity region, the insulating film, and the conductive film.Type: ApplicationFiled: September 26, 2013Publication date: January 30, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki ATSUMI, Hiroki INOUE
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Publication number: 20140014964Abstract: In a semiconductor device, gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage.Type: ApplicationFiled: September 13, 2013Publication date: January 16, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Murakami, Yosuke Tsukamoto, Tomoaki Atsumi, Masayuki Sakakura
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Patent number: 8627170Abstract: An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p?1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.Type: GrantFiled: April 27, 2010Date of Patent: January 7, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masafumi Ito, Tomoaki Atsumi
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Patent number: 8558238Abstract: In a semiconductor device including a digital circuit portion and an analog circuit portion having a capacitor portion provided over a substrate, the capacitor portion is provided with a first wiring, a second wiring and a plurality of blocks each having a plurality of capacitor elements. Further, each the plurality of capacitor elements provided in each block has a semiconductor film having a first impurity region and a plurality of second impurity regions provided apart with the first impurity region interposed therebetween, and a conductive film provided over the first impurity region with an insulating film therebetween. A capacitor is formed from the first impurity region, the insulating film, and the conductive film.Type: GrantFiled: May 23, 2007Date of Patent: October 15, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki Atsumi, Hiroki Inoue
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Patent number: 8536581Abstract: In a semiconductor device, gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage.Type: GrantFiled: March 22, 2012Date of Patent: September 17, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Murakami, Yosuke Tsukamoto, Tomoaki Atsumi, Masayuki Sakakura
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Publication number: 20130069132Abstract: Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.Type: ApplicationFiled: September 7, 2012Publication date: March 21, 2013Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Tomoaki Atsumi, Takashi Okuda
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Patent number: 8305216Abstract: Initialization of a semiconductor device can be efficiently performed, which transmits and receives data through wireless communication. The semiconductor device includes an antenna, a power source circuit, a circuit which uses a DC voltage generated by the power source circuit as a power source voltage, and a resistor. The antenna includes a pair of terminals and receives a wireless signal (a modulated carrier wave). The power source circuit includes a first terminal and a second terminal and generates a DC voltage between the first terminal and the second terminal by using a received wireless signal (the modulated carrier wave). The resistor is connected between the first terminal and the second terminal. In this manner, the semiconductor device and the wireless communication system can transmit and receive data accurately.Type: GrantFiled: September 7, 2011Date of Patent: November 6, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tomoaki Atsumi, Yutaka Shionoiri, Hidetomo Kobayashi
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Publication number: 20120275214Abstract: In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.Type: ApplicationFiled: April 25, 2012Publication date: November 1, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Tomoaki ATSUMI, Yoshiya TAKEWAKI
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Publication number: 20120273773Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.Type: ApplicationFiled: April 11, 2012Publication date: November 1, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yoshinori IEDA, Atsuo ISOBE, Yutaka SHIONOIRI, Tomoaki ATSUMI
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Publication number: 20120235153Abstract: In a semiconductor device, gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage.Type: ApplicationFiled: March 22, 2012Publication date: September 20, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Satoshi Murakami, Yosuke Tsukamoto, Tomoaki Atsumi, Masayuki Sakakura
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Patent number: 8253469Abstract: It is an object of the present invention to provide a semiconductor device that has a simple circuit structure, a small scale, and low power consumption, and can generate a desired clock signal. The semiconductor device has a clock generation circuit which generates a clock signal by dividing a modulated carrier wave, a divider circuit which generates a first divided signal by dividing a carrier wave, and a correction circuit which generates a second divided signal by further dividing the first divided signal, and has a function of performing correction for inverting the second divided signal in a period corresponding to a half period of the clock signal during modulation of the carrier wave and selecting whether the correction is performed or not.Type: GrantFiled: September 28, 2009Date of Patent: August 28, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Tomoaki Atsumi
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Patent number: 8232880Abstract: The present invention provides a battery as a power supply for supplying power in the RFID, and another antenna for charging the battery, in addition to an antenna which transmits and receives individual information to and from outside as a means for supplying power to the battery.Type: GrantFiled: March 9, 2007Date of Patent: July 31, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Masato Ishii, Tomoaki Atsumi, Takeshi Osada, Takayuki Ikeda, Yoshiyuki Kurokawa, Yutaka Shionoiri
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Patent number: 8205801Abstract: A semiconductor device includes a memory portion, a logic portion, and a plurality of signal lines for electrically connecting the memory portion and the logic portion. In the case where a transfer rate between the semiconductor device and a communication device is ? [bps], a first clock frequency generated in the logic portion is K? [Hz] (K is an integer of 1 or more), the number of reading signal lines of the plurality of signal lines is n (n is an integer of 2 or more), and a second clock frequency generated in the logic portion is L?/n [Hz] (L is any integer satisfying L/n<K), data stored in the memory portion is read to the logic portion through the n reading signal lines with use of the second clock frequency L?/n [Hz].Type: GrantFiled: September 30, 2010Date of Patent: June 26, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidetomo Kobayashi, Tomoaki Atsumi, Seiichi Yoneda, Yasuyuki Takahashi, Kiyoshi Kato
