Patents by Inventor Tomoaki Kawai

Tomoaki Kawai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5499362
    Abstract: In an image processing apparatus, when a hard copy of image data displayed on a display with reduced gradation and non-image data displayed on the display is simultaneously produced, the image data are automatically printed as data having original high gradation while being synthesized with the non-image data. When a hard copy of image data and non-image data displayed on a bit-map display having low gradation is produced, the image data having high gradation is printed by a full-color printer by reading original-image data having the high gradation from a hard disk and synthesizing the read data with the non-image data in an image memory by a printer control unit according to image control information stored in an image control table.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 12, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomoaki Kawai, Hiroyuki Yamamoto, Hiroshi Okazaki
  • Patent number: 5444833
    Abstract: In a graphic editor, a graphic pattern is entered by a pointer with the aid of grid points. The size of the grid points is varied over the entire display image or over a portion of the display image according to the type of entering operation.
    Type: Grant
    Filed: February 17, 1993
    Date of Patent: August 22, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomoaki Kawai, Takashi Nakamura, Tsuneaki Kadosawa, Kunitaka Ozawa, Eiji Koga, Satoshi Ogiwara
  • Patent number: 5418919
    Abstract: An information processing device which operates under a multiprogramming system stores instruction words and an execution condition word for each of those instruction words as a pair in program memories, judges whether or not an instruction can be executed on the basis of its execution condition word and executes the instruction when it is judged to be executable. An information processing device which operates under a multi-CPU system connects a plurality of memories to a plurality of CPUs. The plurality of memories store the global variables accessed most frequently by the CPU with which their own memories are connected.
    Type: Grant
    Filed: December 6, 1993
    Date of Patent: May 23, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tsuneaki Kadosawa, Takashi Nakamura, Eiji Koga, Satoshi Ogiwara, Tomoaki Kawai, Kunitaka Ozawa