Abstract: Entrance and exit of a person is efficiently managed by simple authentication and registration of entrance and exit using a communication terminal carried by the person.

Abstract: Entrance and exit of a person is efficiently managed by simple authentication and registration of entrance and exit using a communication terminal carried by the person.

Abstract: Entrance and exit of a person is efficiently managed by simple authentication and registration of entrance and exit using a communication terminal carried by the person.

Abstract: A monitoring device is configured to include an image data acquiring unit, a detecting unit, and a notifying unit. The image data acquiring unit acquires image data obtained by imaging a work area, and information relating to the position in which the image data were captured. The detecting unit detects, from the image data, at least either an unsafe behavior of a worker in the work area, or an unsafe environment around the worker, as an unsafe condition. The notifying unit notifies a terminal of the unsafe condition detected by the detecting unit, and the information relating to the position in which the unsafe condition is detected.

Abstract: Entrance and exit of a person is efficiently managed by simple authentication and registration of entrance and exit using a communication terminal carried by the person.

Abstract: Entrance and exit of a person is efficiently managed by simple authentication and registration of entrance and exit using a communication terminal carried by the person.

Abstract: Entrance and exit of a person is efficiently managed by simple authentication and registration of entrance and exit using a communication terminal carried by the person.

Abstract: In one embodiment of the present invention, an operational amplifier circuit, a switching element is closed and a switching element is opened. A latch circuit DL latches an output voltage of an operational amplifier and supplies a Q output corresponding to the output voltage. A control circuit supplies an offset adjustment signal to an offset adjustment input terminal OR of the operational amplifier, thereby adjusting an offset of the output voltage. The latch circuit DL latches again the output voltage thus adjusted and minutely adjusts the offset adjustment signal so as to adjust the remaining offset. Weighting is carried out in accordance with how many times latching has been carried out, and the offset of the output voltage of the operational amplifier is quantized, thereby obtaining a binary logical signal and storing the signal in the control circuit.

Abstract: The present invention provides an offset adjusting circuit and an operational amplifier circuit. In the operational amplifier circuit (1), a switching element (S1) is closed and a switching element (S2) is opened. The latch circuit DL latches an output voltage of an operational amplifier (1a), and output a Q-output in accordance with the output voltage. The control circuit (2a) inputs an offset adjustment signal s1 to an offset adjustment input terminal OR of the operational amplifier (1a). Then, the latch circuit DL latches the output voltage having been subjected to the offset adjustment, and the offset adjustment signal s1 is finely adjusted for adjusting the remaining offset. In this way, the offset in the output voltage of the operational amplifier (1a) is quantized in accordance with the number of times the latching operation has been performed, and is stored in the control circuit (2a) in the form of a binary logical signal.

Abstract: In one embodiment of the present invention, an operational amplifier circuit, a switching element is closed and a switching element is opened. A latch circuit DL latches an output voltage of an operational amplifier and supplies a Q output corresponding to the output voltage. A control circuit supplies an offset adjustment signal to an offset adjustment input terminal OR of the operational amplifier, thereby adjusting an offset of the output voltage. The latch circuit DL latches again the output voltage thus adjusted and minutely adjusts the offset adjustment signal so as to adjust the remaining offset. Weighting is carried out in accordance with how many times latching has been carried out, and the offset of the output voltage of the operational amplifier is quantized, thereby obtaining a binary logical signal and storing the signal in the control circuit.

Abstract: A P-channel MOS transistor and an N-channel MOS transistor are respectively controlled by a first control signal and a second control signal. The first control signal CTL1 and the second control signal CTL2 are independent from each other. The second control signal CTL2 is generated by a NOR circuit 2 to which a data signal DATA and a third control signal CTL3 are inputted. A load capacitor C1 which samples the first electric potential or the GND electric potential is configured by a gate capacitance of another MOS transistor.

Abstract: Reference voltage generation means is constituted by including first voltage division means constituted so as to be able to generate a plurality of levels of gradation display voltages by resistance-dividing voltage differences between a plurality of reference voltages VR by a plurality of dividing resistors connected in series, second voltage division means constituted so as to be able to generate some or all of the gradation display voltages by resistance-dividing voltage differences between a plurality of reference voltages VR by a plurality of auxiliary resistors connected in series, and switching means for mutually connecting all or a part of the plurality of gradation display voltages generated by the first voltage division means and the second voltage division means. The switching means is turned on during the transient state period in which the DA conversion circuit responds and the first and second voltage division means operate.

Abstract: A display driving integrated circuit includes: a tone display reference voltage generating circuit for generating 64 tone display reference voltages by resistive division on the basis of a predetermined reference voltage; D/A conversion circuits each for performing an analog conversion with respect to display data on the basis of the 64 tone display reference voltages; and 64 reference voltage wires provided in parallel, via which the 64 tone display reference voltages are supplied to the D/A conversion circuits, respectively. The 64 reference voltage wires are provided so that a potential difference corresponds to two tones or more between adjacent two reference voltage wires.

Abstract: The present invention provides an offset adjusting circuit and an operational amplifier circuit. In the operational amplifier circuit (1), a switching element (S1) is closed and a switching element (S2) is opened. The latch circuit DL latches an output voltage of an operational amplifier (1a), and output a Q-output in accordance with the output voltage. The control circuit (2a) inputs an offset adjustment signal s1 to an offset adjustment input terminal OR of the operational amplifier (1a). Then, the latch circuit DL latches the output voltage having been subjected to the offset adjustment, and the offset adjustment signal s1 is finely adjusted for adjusting the remaining offset. In this way, the offset in the output voltage of the operational amplifier (1a) is quantized in accordance with the number of times the latching operation has been performed, and is stored in the control circuit (2a) in the form of a binary logical signal.

Abstract: A P-channel MOS transistor and an N-channel MOS transistor are respectively controlled by a first control signal and a second control signal. The first control signal CTL1 and the second control signal CTL2 are independent from each other. The second control signal CTL2 is generated by a NOR circuit 2 to which a data signal DATA and a third control signal CTL3 are inputted. A load capacitor C1 which samples the first electric potential or the GND electric potential is configured by a gate capacitance of another MOS transistor.

Abstract: Reference voltage generation means is constituted by including first voltage division means constituted so as to be able to generate a plurality of levels of gradation display voltages by resistance-dividing voltage differences between a plurality of reference voltages VR by a plurality of dividing resistors connected in series, second voltage division means constituted so as to be able to generate some or all of the gradation display voltages by resistance-dividing voltage differences between a plurality of reference voltages VR by a plurality of auxiliary resistors connected in series, and switching means for mutually connecting all or a part of the plurality of gradation display voltages generated by the first voltage division means and the second voltage division means. The switching means is turned on during the transient state period in which the DA conversion circuit responds and the first and second voltage division means operate.

Abstract: A device for engaging or disengaging an end fitting of a control cable to or from a lever in a drum brake or the like is arranged to be shorter but to have a large lever ratio for the lever. A shoe is engaged with one end of a strut, and the lever is pivotally journalled to the other end of the strut while another shoe is engaged with the lever at a portion near to the journalled part. The strut has two opposed side walls and a bridge part therebetween for restraining the lever at a specified position. The lever is composed of a pair of planer members which are joined together at the proximal end, and are spaced apart from each other at the free end to form a narrow gap and at the longitudinally middle portion to form a wide gap. The narrow gap allows a cable itself of the cable to pass therethrough but to inhibit from passing therethrough and the wide gap allows a longer side of the end fitting to pass therethrough.

Abstract: A sending LSI of a signal transmission system is provided with a synthesizing section for producing a multivalued logic signal by synthesizing a clock signal with a data signal in sync with the clock signal. In the meantime, a receiving LSI of the signal transmission system is provided with a separation section for separating the multivalued logic signal, which has been transmitted from the sending LSI, into the original clock signal and data signal. With this arrangement, it is possible to eliminate the constraint of a setup/hold period in the receiving end, without providing complicated synchronizing circuits such as a PLL circuit in the logic circuit of the receiving end.

Abstract: A DA converter is for converting N-bit digital signals to 2N analog signals, and includes a reference voltage generating circuit for generating the reference voltages having 2A+1 voltage levels, a reference voltage selector circuit for selecting two reference voltages having adjacent voltage levels according to the A bits of a digital signal, an output voltage selector circuit for selecting one interpolation voltage from 2N-A−1 interpolation voltages predetermined between the voltage levels of the two reference voltages in accordance with the N-A bits of the digital signal, and a voltage follower circuit for producing the above interpolation voltage by linear interpolation based on the two reference voltages.

Abstract: There is provided a gray scale display reference voltage generating circuit that can change a gamma correction characteristic in accordance with a liquid crystal material and LCD panel characteristics. Resistor elements R0 through R7 have a resistance ratio for gamma correction and generate gamma-corrected intermediate voltages on the basis of voltages across both input terminals V0 and V64. A gamma correction adjustment circuit 42 adjusts the gamma-corrected intermediate voltages upward or downward on the basis of adjustment data latched in a data latch circuit 43. By thus supplying the adjustment data corresponding to the liquid crystal material and the LCD panel characteristics to the data latch circuit 43, the gamma correction characteristic can be changed in accordance with the liquid crystal material and the LCD panel characteristics without modifying the design of a source driver.