Patents by Inventor Tomoaki Nakao

Tomoaki Nakao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6437716
    Abstract: There is provided a gray scale display reference voltage generating circuit that can change a gamma correction characteristic in accordance with a liquid crystal material and LCD panel characteristics. Resistor elements R0 through R7 have a resistance ratio for gamma correction and generate gamma-corrected intermediate voltages on the basis of voltages across both input terminals V0 and V64. A gamma correction adjustment circuit 42 adjusts the gamma-corrected intermediate voltages upward or downward on the basis of adjustment data latched in a data latch circuit 43. By thus supplying the adjustment data corresponding to the liquid crystal material and the LCD panel characteristics to the data latch circuit 43, the gamma correction characteristic can be changed in accordance with the liquid crystal material and the LCD panel characteristics without modifying the design of a source driver.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: August 20, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomoaki Nakao
  • Patent number: 6373419
    Abstract: A standard voltage generating circuit produces 2(N−1)+1 mutually different standard voltages. A selector circuit stores standard voltage pairs so that each of the digital signals corresponds to one of the standard voltage pairs. No standard voltage pairs produce the same mean value. Upon reception of an input digital signal, the selector circuit selects one of the standard voltage pairs which corresponds to the input digital signal and provides the standard voltages of the selected pair for output. The standard voltages provided for output by the selector circuit are supplied to a voltage follower circuit which provides an output voltage having a mean value of the input standard voltages.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: April 16, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomoaki Nakao
  • Publication number: 20020033763
    Abstract: A DA converter is for converting N-bit digital signals to 2N analog signals, and includes a reference voltage generating circuit for generating the reference voltages having 2A+1 voltage levels, a reference voltage selector circuit for selecting two reference voltages having adjacent voltage levels according to the A bits of a digital signal, an output voltage selector circuit for selecting one interpolation voltage from 2N-A−1 interpolation voltages predetermined between the voltage levels of the two reference voltages in accordance with the N-A bits of the digital signal, and a voltage follower circuit for producing the above interpolation voltage by linear interpolation based on the two reference voltages.
    Type: Application
    Filed: July 25, 2001
    Publication date: March 21, 2002
    Inventor: Tomoaki Nakao
  • Patent number: 6331846
    Abstract: An incidental offset voltage caused by discrepancies in material and workmanship can be averaged by (1) using two input transistors of a differential amplifier alternately, and (2) switching output signals from both the input transistors through two switches provided to an output end. Consequently, a downsized, less-power-consuming, highly-reliable differential amplifier which is insensitive to an incidental offset voltage caused by discrepancies in material and workmanship can be provided. Also, by employing such a differential amplifier, a less-power-consuming and highly reliable operational amplifier and a liquid crystal driving circuit capable of showing display of an upgraded quality can be realized.
    Type: Grant
    Filed: April 14, 1999
    Date of Patent: December 18, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomoaki Nakao
  • Patent number: 6310593
    Abstract: A liquid crystal driving circuit includes: a charge capacitor and a distribution capacitor, each having a first electrode and a second electrode, respective first electrodes of the charge capacitor and the distribution capacitor being connected to each other; a first switch for connecting and disconnecting respective second electrodes of the charge capacitor and the distribution capacitor; a select switch for selecting application of a first reference voltage and a second reference voltage with respect to the second electrode of the charge capacitor by connection or disconnection; an operational amplifier for outputting an analog signal for multi-tone display in accordance with an amount of charge of the distribution capacitor and the second reference voltage; and a controller for alternately controlling the first switch and the select switch in accordance with a digital signal for multi-tone display.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: October 30, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomoaki Nakao
  • Publication number: 20010003431
    Abstract: There is provided a gray scale display reference voltage generating circuit that can change a gamma correction characteristic in accordance with a liquid crystal material and LCD panel characteristics. Resistor elements R0 through R7 have a resistance ratio for gamma correction and generate gamma-corrected intermediate voltages on the basis of voltages across both input terminals V0 and V64. A gamma correction adjustment circuit 42 adjusts the gamma-corrected intermediate voltages upward or downward on the basis of adjustment data latched in a data latch circuit 43. By thus supplying the adjustment data corresponding to the liquid crystal material and the LCD panel characteristics to the data latch circuit 43, the gamma correction characteristic can be changed in accordance with the liquid crystal material and the LCD panel characteristics without modifying the design of a source driver.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 14, 2001
    Inventor: Tomoaki Nakao
  • Patent number: 6160533
    Abstract: A reference voltage having a plurality of voltage levels which increase stepwise over time is supplied to source lines on a display panel through a plurality of analog switches. A value representing a number of gradation display data levels for the source lines during a horizontal scanning period is supplied as one input in to a comparison circuit. A count registered by a counter and representing a gradation clock signal is supplied as a second input. Where the count is less than the value, the analog switches remain conducted. Once the count equals to or exceeds the value, the analog switches are cut off, thus enabling the supplied reference voltage to be applied as a driving voltage to a pair of pixel electrodes. The driving voltage corresponds to the number of gradation display data levels and is held constant at the pixel electrodes for the remaining horizontal scanning period.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: December 12, 2000
    Assignee: Sharp Kabushiki Kaishi
    Inventors: Shigeki Tamai, Tomoaki Nakao
  • Patent number: 5796615
    Abstract: In a correcting method of an automobile's door frame by applying a conventional correcting unit, tightening method to securely fix hinges of the door frame by means of jigs is developed, as well as clampers, and the door frame is supported by three points such as two hinges and a damper as if in the same manner as the door frame is supported by two hinges and a door lock in actual installation in a car when the door frame is inspected. The door frame is also slightly touched by a floating unit on an upper corner of reaward edge of the door frame when the door frame is corrected, preventing a slight distortion generated during the correcting operation from being unfairly enlarged. 12 patterns combinations of parameters and 20 correcting approximate equations are prepared.
    Type: Grant
    Filed: May 8, 1996
    Date of Patent: August 18, 1998
    Assignee: Hirotec Corporation
    Inventors: Takashi Madaraishi, Tomoaki Nakao, Ryoji Tanaka
  • Patent number: 5751186
    Abstract: An operational amplifier circuit 21 comprises transistors N14, N15 in a first output amplifier circuit 24, and transistors P24, P25 in a second output amplifier circuit 25. When a second differential amplifier circuit 23 is cut off, the output is driven by transistor P13 and transistors N14, N15. When a first differential amplifier circuit 22 is cut off, the output is driven by transistor N23 and transistors P24, P25. Therefore, if such a voltage as to cut off one differential amplifier circuit is given from opposite phase and in-phase input terminals 31, 32, the output can be produced. In such constitution, without using depletion type transistors that require particular manufacturing process, the range of the voltage that can be entered in the input terminal can be extended.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: May 12, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomoaki Nakao
  • Patent number: 5332936
    Abstract: When a transistor 1 is turned off, and transistors 5 and 7 are both turned on, first and second output signals Oa and Ob both attain a first potential GND irrespective of the logic level of a second logic signal Ib and a third logic signal /Ib. When the transistor 1 is turned on and the transistors 5 and 7 are both turned off by the first logic signal Ia, a transistor 4 is turned off and a transistor 6 is turned on, whereby first and second output signals Oa and Ob attain a second potential VEE and the first potential GND, respectively. When the transistor 1 is turned on, and transistors 5 and 7 are turned off, the transistor 4 is turned on and the transistor 6 is turned off, whereby the first and second output signals Oa and Ob attain the first potential GND and the second potential VEE, respectively. Thus a composite logic circuit can be implemented with 7 transistors.
    Type: Grant
    Filed: April 14, 1993
    Date of Patent: July 26, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomoaki Nakao
  • Patent number: 5289518
    Abstract: A logic circuit for outputting signals corresponding to an input signal depending on a clock signal sent from an external source includes at least one synchronous flip-flop being synchronized with the clock signal, so that the flip-flop latches the input signal, and a unit for controlling an input of the clock signal to the flip-flop based on a difference between logic levels of an output signal of the flip-flop and an input signal newly latched by the flip-flop.
    Type: Grant
    Filed: February 5, 1992
    Date of Patent: February 22, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomoaki Nakao