Patents by Inventor Tomohiko Otose
Tomohiko Otose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7665816Abstract: The invention provides a semiconductor device of low power consumption and low cost. A semiconductor device 50 is basically constituted of a semiconductor substrate 1 and an external signal processing substrate 8. The semiconductor substrate 1 is provided with a memory unit 3, a data driver 4, an element array 2, a scanning circuit 35 and a clock generator 36. When successively outputting an identical data signal to the element array 2 over a plurality of times, the data signal retained in the memory unit 3 is utilized.Type: GrantFiled: January 13, 2006Date of Patent: February 23, 2010Assignee: NEC CorporationInventor: Tomohiko Otose
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Publication number: 20090290677Abstract: Disclosed is a shift register which includes first transistor connected between a first clock signal terminal and an output terminal, a second transistor with a gate connected to an input terminal and a source connected to a gate of the first transistor, a third transistor with a gate connected to a second clock signal terminal, an inverter with an input connected to the input terminal, a fourth transistor cascode connected to the third transistor with a gate connected to an output of the inverter, a fifth transistor connected between the gate of the first transistor and a power supply terminal, a sixth transistor connected between the fourth transistor and the power supply terminal with a gate connected to the input terminal, and a seventh transistor connected between the output terminal and the power supply terminal, the fifth and seventh transistors having gates connected in common to a connection node of the fourth and the sixth transistors.Type: ApplicationFiled: May 22, 2009Publication date: November 26, 2009Applicant: NEC LCD Technologies, Ltd.Inventors: Tomohiko Otose, Masamichi Shimoda
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Patent number: 7612856Abstract: A display device includes: a pair of substrates disposed opposite each other; a conductive seal for sealing the gap of the outer peripheral part between the pair of substrates; an electric optical element disposed in an area defined by the substrates and the seal; a display area, formed on one substrate, having a plurality of pixels for controlling the electric optical element; and a driver circuit for controlling the pixels. The driver circuit is so configured that a circuit element affected by stray capacitance formed between the conductive seal and the driver circuit is disposed apart from the conductive seal.Type: GrantFiled: March 28, 2006Date of Patent: November 3, 2009Assignees: NEC LCD Technologies, Ltd., NEC CorporationInventors: Tomohiko Otose, Koji Shigemura
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Publication number: 20090115792Abstract: A device, in which circuit size is small and operation is stable, comprises a plurality of serially connected unit registers (shift registers) in which transfer is controlled by any of three or more clock signals each having a different phase, and a setting signal which determines shift direction; and a selection circuit (switch array) which can select at least one clock signal from the three or more clock signals in accordance with the setting signal; wherein the unit registers are put in a reset state by one clock signal selected by the selection circuit, corresponding to each of the unit registersType: ApplicationFiled: November 4, 2008Publication date: May 7, 2009Applicant: NEC LCE TECHNOLOGIES, LTD.Inventors: Tomohiko OTOSE, Masamichi Shimoda
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Publication number: 20090021466Abstract: Disclosed is a display apparatus including two scanning circuits of the same configuration and layout, arranged on either sides of the display part. As long as one of the scanning circuits is in operation, the other scanning circuit is in a state in which no output signal is output.Type: ApplicationFiled: July 17, 2008Publication date: January 22, 2009Applicant: NEC LCD TECHNOLOGIES, LTD.Inventors: Tomohiko OTOSE, Masamichi Shimoda
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Publication number: 20080123799Abstract: Disclosed is a semiconductor circuit in which a floating node is set to any voltage by utilizing a control signal which is applied to a refresh terminal and has a period shorter than that of a clock signal. The semiconductor circuit includes first and second transistors connected between a first clock terminal and a first power supply terminal, third and fourth transistors connected between the refresh terminal and the first power supply terminal, and fifth and sixth transistors connected between a second power supply terminal and the first power supply. Gates of the fourth and fifth transistors are connected in common to an input terminal, a gate of the third transistor is connected to a second clock terminal, a gate of the first transistor is connected to a connection node between the fifth and sixth transistors, the gate of the second transistor is connected to the gate of the sixth transistor, and a connection node between the first and second transistors is connected to an output terminal.Type: ApplicationFiled: November 27, 2007Publication date: May 29, 2008Applicant: NEC LCD TECHNOLOGIES, LTD.Inventor: Tomohiko OTOSE
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Patent number: 7355323Abstract: A piezoelectric device includes a flexible substrate and a piezoelectric element including a pair of electrodes each positioned on the flexible substrate. A switching element is connected to one of the pair of electrodes, in the flexible substrate, and a common line is connected to the other of the pair of electrodes, on the flexible substrate.Type: GrantFiled: July 25, 2005Date of Patent: April 8, 2008Assignee: NEC CorporationInventor: Tomohiko Otose
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Publication number: 20060215102Abstract: A display device includes: a pair of substrates disposed opposite each other; a conductive seal for sealing the gap of the outer peripheral part between the pair of substrates; an electric optical element disposed in an area defined by the substrates and the seal; a display area, formed on one substrate, having a plurality of pixels for controlling the electric optical element; and a driver circuit for controlling the pixels. The driver circuit is so configured that a circuit element affected by stray capacitance formed between the conductive seal and the driver circuit is disposed apart from the conductive seal.Type: ApplicationFiled: March 28, 2006Publication date: September 28, 2006Inventors: Tomohiko Otose, Koji Shigemura
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Publication number: 20060119634Abstract: The invention provides a semiconductor device of low power consumption and low cost. A semiconductor device 50 is basically constituted of a semiconductor substrate 1 and an external signal processing substrate 8. The semiconductor substrate 1 is provided with a memory unit 3, a data driver 4, an element array 2, a scanning circuit 35 and a clock generator 36. When successively outputting an identical data signal to the element array 2 over a plurality of times, the data signal retained in the memory unit 3 is utilized.Type: ApplicationFiled: January 13, 2006Publication date: June 8, 2006Applicant: NEC CORPORATIONInventor: Tomohiko Otose
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Publication number: 20060109225Abstract: A device excellent in electrical characteristics is provided by suppressing an operation failure owing to a hysteresis effect that occurs in a circuit using MOS transistors having floating bodies. Moreover, sensitivity of a sense amplifier circuit and a latch circuit including these MOS transistors as components is improved. A signal required in a circuit other than a first circuit is outputted by using electrical characteristics of MOS transistors in a first period (effective period), and in a second period (idle period) excluding the first period, between the gate and source of MOS transistors, a step waveform voltage not less than threshold voltages of these MOS transistors is given.Type: ApplicationFiled: September 19, 2005Publication date: May 25, 2006Inventors: Hiroshi Haga, Tomohiko Otose, Hideki Asada, Yoshihiro Nonaka, Takahiro Korenari, Kenichi Takatori
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Patent number: 7012849Abstract: The invention provides a semiconductor device of low power consumption and low cost. A semiconductor device 50 is basically constituted of a semiconductor substrate 1 and an external signal processing substrate 8. The semiconductor substrate 1 is provided with a memory unit 3, a data driver 4, an element array 2, a scanning circuit 35 and a clock generator 36. When successively outputting an identical data signal to the element array 2 over a plurality of times, the data signal retained in the memory unit 3 is utilized.Type: GrantFiled: July 16, 2003Date of Patent: March 14, 2006Assignee: Nec CorporationInventor: Tomohiko Otose
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Publication number: 20060017351Abstract: A piezoelectric device includes a flexible substrate and a piezoelectric element including a pair of electrodes each positioned on the flexible substrate. A switching element is connected to one of the pair of electrodes, in the flexible substrate, and a common line is connected to the other of the pair of electrodes, on the flexible substrate.Type: ApplicationFiled: July 25, 2005Publication date: January 26, 2006Applicant: NEC CORPORATIONInventor: Tomohiko Otose
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Publication number: 20060012543Abstract: A light-detecting element, an analog-to-digital converter circuit, and a parallel-serial converter circuit are mounted on a substrate, using a thin film transistor, of an active matrix-type display device, and when a circuit is selected by an external chip-select signal, the luminance is adjusted by transmitting a signal of the light-detecting element, converted into digital data, to a luminance control circuit in sync with a clock signal.Type: ApplicationFiled: July 13, 2005Publication date: January 19, 2006Applicant: NEC CorporationInventors: Naoyasu Ikeda, Hiroshi Haga, Tomohiko Otose, Tatsuya Uchikawa, Daisuke Suzuki
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Patent number: 6750895Abstract: An optical printer head with a plurality of light-emitting devices arranged in two dimensions is capable of providing a desired amount of exposure using light-emitting devices having even small luminance, ease of corrections to a sensitivity of a photosensitive body and to a positional displacement of an object to be printed, performing printing on multiple gray scales and implementing high density and miniaturization. The optical printer head is so configured that a picture element array including picture elements containing light-emitting devices arranged in line and string directions in two dimensions, a horizontal scanning circuit to feed data signals to each picture element string in the picture element array and a vertical scanning circuit to sequentially select and activate each picture element in the picture element array are formed on a same insulating substrate to support production of the above effects.Type: GrantFiled: September 29, 2000Date of Patent: June 15, 2004Assignee: NEC CorporationInventors: Tomohiko Otose, Hideki Asada, Tsutomu Uezono, Atsushi Oda, Satoru Toguchi
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Publication number: 20040013019Abstract: The invention provides a semiconductor device of low power consumption and low cost.Type: ApplicationFiled: July 16, 2003Publication date: January 22, 2004Applicant: NEC CORPORATIONInventor: Tomohiko Otose
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Patent number: 6642950Abstract: An optical printer head usable in an optical printer with a line light source and suitably utilizing an organic electroluminscence (EL) element and the like as its light-emitting element that includes a pixel array including pixels arranged two-dimensionally in row and column directions, each of the pixels including a light-emitting element, a memory array including memory cells arranged two-dimensionally in row and column directions for holding printing data input thereto, a horizontal scanning circuit for supplying a data signal to each memory cell column, a first vertical scanning circuit for sequentially selecting memory cell rows to write data to each memory cell, a circuit for arbitrarily selecting the memory cell rows to read data from each memory cell, a second vertical scanning circuit for sequentially selecting pixel rows, and a buffer located between the memory array and the pixel array.Type: GrantFiled: April 17, 2001Date of Patent: November 4, 2003Assignee: NEC CorporationInventors: Tomohiko Otose, Hideki Asada
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Publication number: 20010033323Abstract: An optical printer head usable in an optical printer with a line light source and suitably utilizing an organic electroluminescence (EL) element and the like as its light-emitting element. The optical printer head comprises a pixel array including pixels arranged two-dimensionally in row and column directions, each of the pixels including a light-emitting element, a memory array including memory cells arranged two-dimensionally in row and column directions for holding printing data input thereto, a horizontal scanning circuit for supplying a data signal to each memory cell column, a first vertical scanning circuit for sequentially selecting memory cell rows to write data to each memory cell, a circuit for arbitrarily selecting the memory cell rows to read data from each memory cell, a second vertical scanning circuit for sequentially selecting pixel rows, and a buffer located between the memory array and the pixel array.Type: ApplicationFiled: April 17, 2001Publication date: October 25, 2001Inventors: Tomohiko Otose, Hideki Asada