Patents by Inventor Tomohiko Sato

Tomohiko Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190210949
    Abstract: To provide a method capable of easily and efficiently removing a 2-alkoxyethanol from a mixture containing the 2-alkoxyethanol and a (2-alkoxyethyl) vinyl ether while suppressing a decrease in the yield of (2-alkoxyethyl) vinyl ether. A method for removing a 2-alkoxyethanol, including the step of adding one or more azeotropic solvents selected from the group consisting of alkanes having 7 to 8 carbon atoms and cycloalkanes having 7 to 8 carbon atoms to a mixture containing the 2-alkoxyethanol represented by the following formula (1) R—O—CH2CH2OH??(1) where R represents an alkyl group having 1 to 4 carbon atoms, and a (2-alkoxyethyl) vinyl ether represented by the following formula (2) R—O—CH2CH2O—CH?CH2??(2) where R has the same meaning as R in the formula (1), and subjecting the resulting mixture to azeotropic distillation.
    Type: Application
    Filed: September 13, 2017
    Publication date: July 11, 2019
    Applicant: MARUZEN PETROCHEMICAL CO., LTD.
    Inventors: Takashi NANIKI, Ryuichi TENJIMBAYASHI, Masuo YAMAZAKI, Tomohiko SATO
  • Patent number: 9825160
    Abstract: A semiconductor device includes: a semiconductor substrate; a main electrode; a peripheral electrode; an insulating protective film; a surface metallic layer; and a solder layer, wherein the semiconductor substrate includes: a first region of a first conductive-type in contact with the main electrode on a main contact surface; a second region of a first conductive-type in contact with the peripheral electrode on a peripheral contact surface; and a third region of a second conductive-type provided under the first region, under the second region, and circumferentially outward of the second region, and a circumferentially-outward end of the metallic layer and a circumferentially-outward end of the solder layer are located more circumferentially inward than the circumferentially-outward end of the peripheral electrode.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: November 21, 2017
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Tomohiko Sato
  • Publication number: 20170243964
    Abstract: A semiconductor device includes: a semiconductor substrate; a main electrode; a peripheral electrode; an insulating protective film; a surface metallic layer; and a solder layer, wherein the semiconductor substrate includes: a first region of a first conductive-type in contact with the main electrode on a main contact surface; a second region of a first conductive-type in contact with the peripheral electrode on a peripheral contact surface; and a third region of a second conductive-type provided under the first region, under the second region, and circumferentially outward of the second region, and a circumferentially-outward end of the metallic layer and a circumferentially-outward end of the solder layer are located more circumferentially inward than the circumferentially-outward end of the peripheral electrode.
    Type: Application
    Filed: February 16, 2017
    Publication date: August 24, 2017
    Inventor: Tomohiko Sato
  • Patent number: 9715728
    Abstract: In order to provide a tomographic image analyzing apparatus which is simple and which obtains stable results, the tomographic image analyzing apparatus according to this invention includes an image standardizing unit which transforms PET images, in advance of tomographic image analysis, so that the contour of the brain of an subject appearing in the PET images become the contour of a brain represented by standard data. By carrying out such transforming operation before the analysis, there is no need to acquire MRI images like before, to be able to ease the burden on the subject. And according to this invention, the time of analysis is shortened. Further, according to this invention, an analysis of time variations of radioactive drug distribution is conducted with respect to a corresponding site on standardized PET images which corresponds to the ROI on the standard data. This can make analysis results stable.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: July 25, 2017
    Assignees: SHIMADZU CORPORATION, THE UNIVERSITY OF TOKYO, FUJIFILM RI PHARMA CO., LTD.
    Inventors: Toshimitsu Momose, Tomohiko Sato, Tsutomu Soma, Daisuke Saito, Miwako Takahashi, Keisuke Ogaki
  • Patent number: 9607961
    Abstract: A semiconductor device includes a semiconductor substrate, a front surface electrode provided on a front surface of the semiconductor substrate, a solder layer, and a metal member fixed to a front surface of the front surface electrode via the solder layer. The solder layer includes an inner solder portion positioned inner than an end portion of the metal member and an outer solder portion positioned outer than the end portion of the metal member, relative to a direction along the front surface of the semiconductor substrate. The semiconductor substrate includes an inner substrate portion positioned below the inner solder portion and an outer substrate portion positioned below the outer solder portion. A density of carriers that flow from the outer substrate portion to the front surface electrode is lower than a density of carriers that flow from the inner substrate portion to the front surface electrode.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: March 28, 2017
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Tomohiko Sato
  • Publication number: 20160260678
    Abstract: A semiconductor device includes a semiconductor substrate, a front surface electrode provided on a front surface of the semiconductor substrate, a solder layer, and a metal member fixed to a front surface of the front surface electrode via the solder layer. The solder layer includes an inner solder portion positioned inner than an end portion of the metal member and an outer solder portion positioned outer than the end portion of the metal member, relative to a direction along the front surface of the semiconductor substrate. The semiconductor substrate includes an inner substrate portion positioned below the inner solder portion and an outer substrate portion positioned below the outer solder portion. A density of carriers that flow from the outer substrate portion to the front surface electrode is lower than a density of carriers that flow from the inner substrate portion to the front surface electrode.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 8, 2016
    Inventor: Tomohiko Sato
  • Publication number: 20150235358
    Abstract: In order to provide a tomographic image analyzing apparatus which is simple and which obtains stable results, the tomographic image analyzing apparatus according to this invention includes an image standardizing unit which transforms PET images, in advance of tomographic image analysis, so that the contour of the brain of an subject appearing in the PET images become the contour of a brain represented by standard data. By carrying out such transforming operation before the analysis, there is no need to acquire MRI images like before, to be able to ease the burden on the subject. And according to this invention, the time of analysis is shortened. Further, according to this invention, an analysis of time variations of radioactive drug distribution is conducted with respect to a corresponding site on standardized PET images which corresponds to the ROI on the standard data. This can make analysis results stable.
    Type: Application
    Filed: August 28, 2013
    Publication date: August 20, 2015
    Applicants: SHIMADZU CORPORATION, FUJIFILM RI PHARMA CO., LTD., THE UNIVERSITY OF TOKYO
    Inventors: Toshimitsu Momose, Tomohiko Sato, Tsutomu Soma, Daisuke Saito, Miwako Takahashi, Keisuke Ogaki
  • Patent number: 8952553
    Abstract: The present teaching provides a semiconductor device capable of relaxing stress transferred to a contact region during wire bonding and improving reliability of wire bonding. A semiconductor device comprises contact regions, an interlayer insulating film, an emitter electrode, and a stress relaxation portion. The contact regions are provided at a certain interval in areas exposing at a surface of a semiconductor substrate. The interlayer insulating film is provided on the surface of the semiconductor substrate between adjacent contact regions. The emitter electrode is provided on an upper side of the semiconductor substrate and electrically connected to each of the contact regions. The stress relaxation portion is provided on an upper surface of the emitter electrode in an area only above the contact regions. The stress relaxation portion is formed of a conductive material.
    Type: Grant
    Filed: February 16, 2009
    Date of Patent: February 10, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Masaru Senoo, Tomohiko Sato
  • Patent number: 8946813
    Abstract: In a switching element, a first region that is exposed on an upper surface of a semiconductor substrate, a second region that is exposed on the upper surface of the substrate and extends to below the first region, and a third region that is formed below the second region, are formed on the substrate. A trench is formed in the upper surface of the substrate. A gate electrode has a first portion that extends from a depth of the first region to a depth of the third region at at least a portion in the trench formed in an area where the first region is exposed, and a second portion that is formed to a depth of the second region, and does not reach the depth of the third region, at at least a portion in the trench formed in an area where the second region is exposed.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: February 3, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Tomohiko Sato
  • Patent number: 8866717
    Abstract: A display device having a pixel section including a plurality of pixel circuits arrayed in a matrix, a plurality of scan lines, a plurality of capacity lines, a plurality of signal lines, a drive circuit, and a generation circuit generating a small amplitude common voltage signal switching in level at a predetermined cycle, wherein each pixel circuit arranged at the pixel section contains a display element having a first pixel electrode and a second pixel electrode and a storage capacitor having a first electrode and a second electrode, the first pixel electrode of the display element, the first electrode of the storage capacitor, and one terminal of the switching element are connected, the second electrode of the storage capacitor is connected to the capacity lines arrayed in a corresponding row, and the common voltage signal is applied in a second pixel electrode of the display element.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: October 21, 2014
    Assignee: Japan Display, Inc.
    Inventors: Naoyuki Itakura, Tomoyuki Fukano, Yoshiharu Nakajima, Tomohiko Sato, Takeya Takeuchi
  • Patent number: 8837233
    Abstract: A semiconductor device includes first and second bit lines, and a transistor coupled between the first and second bit lines. The semiconductor device further includes a substrate bias control circuit that supplies one of a first substrate bias voltage and a second substrate bias voltage to the transistor. By controlling the substrate bias voltage of the transistor, high-speed equalization is performed, and an increase in leak current at times of standby and activation is prevented.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: September 16, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Tomohiko Sato
  • Publication number: 20140138738
    Abstract: A semiconductor device includes: a channel region, having: a first trench gate, in which a bottom end in a depth direction protrudes into a first drift region, and a non-channel region, having: a second trench gate, in which a bottom end in the depth direction protrudes into a second drift region, that is adjacent to the first trench gate, and protruding length of the second trench gate is shorter than the protruding length of the first trench gate that protrudes into the first drift region.
    Type: Application
    Filed: October 29, 2013
    Publication date: May 22, 2014
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Tomohiko SATO
  • Patent number: 8723786
    Abstract: The present invention provides a liquid crystal display device including: a pixel array including a plurality of scanning lines arranged in rows, a plurality of signal lines arranged in columns, a plurality of liquid crystal elements arranged in a matrix corresponding to an intersection of each scanning line and each signal line, and a plurality of common connection lines arranged one by one corresponding to the liquid crystal elements of each line; a scanning line drive circuit; a signal line drive circuit; and a common connection line drive circuit electrically separating, from each other, one or a plurality of common connection lines (first common connection lines), and a plurality of common connection lines (second common connection lines), and electrically connecting the plurality of second common connection lines to each other to independently drive the first common connection line and the second connection lines from each other.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: May 13, 2014
    Assignee: Japan Display West Inc.
    Inventors: Takeya Takeuchi, Werapong Jarupoonphol, Tomohiko Sato, Yoshitoshi Kida
  • Patent number: 8675437
    Abstract: A semiconductor device includes a plurality of bank sets and an address controller. Each bank set includes a plurality of banks. Each bank includes a plurality of memory mats and sense amplifier arrays corresponding to row addresses. The plurality of bank sets is arranged in both sides of arrays of power electrode pads to be used for operations of the sense amplifier arrays. The plurality of bank sets commonly shares the arrays of power electrode pads. The address controller generates different row addresses that are supplied to different ones of the plurality of bank sets. The different row addresses designate different memory mats in the different ones of the plurality of bank sets, so as to designate different arrays of the power electrode pads for the different ones of the plurality of bank sets for refresh operation in accordance with an external refresh command.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: March 18, 2014
    Inventor: Tomohiko Sato
  • Patent number: 8466867
    Abstract: A liquid crystal display device is provided, which may reduce flicker in all display gray levels. The liquid crystal display device includes a scan line drive circuit, a signal line drive circuit and a common connection line drive circuit. The common connection line drive circuit applies a voltage, the voltage having polarity opposite to polarity of the signal line, to a common connection line corresponding to a liquid crystal element as a selection object in a write period for writing into the liquid crystal element as a selection object, and applies one or multiple voltages, each voltage having a value different from a center value between an upper limit value and a lower limit value of voltages applied to the common connection lines in the write period, to the common connection lines in a holding period after writing into the liquid crystal element as a selection object is performed.
    Type: Grant
    Filed: July 1, 2010
    Date of Patent: June 18, 2013
    Assignee: Japan Display West Inc.
    Inventors: Werapong Jarupoonphol, Takeya Takeuchi, Tomohiko Sato
  • Patent number: 8435892
    Abstract: It is an object of an invention disclosed in the present specification to provide a transistor having low contact resistance. In the transistor, a semiconductor film including an impurity element imparting P-type or N-type conductivity, an insulating film formed thereover, and an electrode or a wiring that is electrically connected to the semiconductor film through a contact hole formed at least in the insulating film are included; the semiconductor film has a first range of a concentration of the impurity element (1×1020/cm3 or less) that is included in a deeper region than predetermined depth, and a second range of a concentration of the impurity element (more than 1×1020/cm3) that is included in a shallower region than the predetermined depth; and a deeper region than a portion in contact with the electrode or the wiring in the semiconductor film is in the first range of the concentration of the impurity element.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: May 7, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Keiko Saito, Tomohiko Sato
  • Publication number: 20120307573
    Abstract: A semiconductor device includes first and second bit lines, and a transistor coupled between the first and second bit lines. The semiconductor device further includes a substrate bias control circuit that supplies one of a first substrate bias voltage and a second substrate bias voltage to the transistor. By controlling the substrate bias voltage of the transistor, high-speed equalization is performed, and an increase in leak current at times of standby and activation is prevented.
    Type: Application
    Filed: August 15, 2012
    Publication date: December 6, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Tomohiko SATO
  • Publication number: 20120302377
    Abstract: A golf ball provided with elliptical dimples. A golf ball provided with non-circular dimples, configured by forming the dimples in the surface of a sphere or of a pseudosphere which consists of a polyhedron. The dimples have a non-circular shape which has a major axis having a length at least 1.2 times greater than that of the minor axis of the shape, are each composed of a pair of circular arcs, and have a depth which causes the peripheral edges of the dimples to generate turbulence. The configuration reduces the separation width at the separation boundary to a level less than that of a golf ball having circular dimples, and this decreases the drag. The polyhedron can be substantially composed of triangles, pentagons, or hexagons.
    Type: Application
    Filed: June 9, 2010
    Publication date: November 29, 2012
    Inventors: Tomohiko Sato, Sunao Umemura, Yutaka Kawata, Mitsuhiro Saso
  • Patent number: D662622
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: June 26, 2012
    Assignee: Toshiba Lighting & Technology Corporation
    Inventors: Junichiro Yamamoto, Shigeru Osawa, Yuichiro Takahara, Tomohiko Sato
  • Patent number: D685505
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 2, 2013
    Assignee: Toshiba Lighting & Technology Corporation
    Inventors: Junichiro Yamamoto, Shigeru Osawa, Yuichiro Takahara, Tomohiko Sato