Abstract: An address counter circuit comprises a first address output circuit for outputting an input address at a first timing, an additional circuit for adding a predetermined value to the input address while the address is output from the first output circuit, a counter circuit for counting up or down the address to which the predetermined value is added by the adding circuit, and a second address output circuit for sequentially outputting addresses obtained upon count-up or count-down operation of the counter circuit after the first timing.

Abstract: The cutoff process of a collector current of an insulated gate transistor is divided into an emitter-to-collector voltage recovery period and a collector current cutoff period. During the emitter-to-collector voltage recovery period the resistance of a gate resistor of the transistor is reduced, and during the collector current cutoff period the resistance of the gate resistor is increased. With this arrangement, the cutoff time is shortened, thereby reducing switching loss and suppressing surge voltage.

Abstract: A clock signal generating circuit is capable of testing a delay line loop (DLL) circuit by a method wherein, when an LSI circuit operates at a lower speed for a burn-in test, etc., the DLL circuit performs the same operation as when the LSI circuit operates normally at a high speed. This invention includes a selector for selecting either a reference clock signal or a test clock signal having a different phase with respect to the reference clock signal, and a delay line loop system phase-locked loop circuit for giving a delay to an output signal of the selector so as to get rid of a phase difference between the reference clock signal and an internal clock signal that has been propagated through a circuit to be supplied with a clock, and for generating the clock signal to be supplied to the circuit.

Abstract: A BiNMOS inverter and a BiCMOS inverter are utilized. The BiNMOS inverter uses first and second power sources. A potential of the second power source is greater than that of the first power source. The BiNMOS has a first bipolar transistor whose collector being connected to the first power source and whose emitter being connected to an output node, and a first P-type field effect transistor group having at least one P-type field effect transistor through which a drain-source current channel consists of the base of the first bipolar transistor and the second power source based on an input signal transmitted to at lease one input node.