Abstract: A ?? modulator includes: an integrator having an operational amplifier and an integral capacitor; a quantizer outputting a quantization result; a D/A converter connected to a first input terminal of the operational amplifier through a first control switch, and subtracting an electric charge based on the quantization result from an electric charge stored in the integral capacitor to perform feedback of the quantization result to the integrator; a control circuit outputting a digital output value; and a sampling capacitor being connected to the first input terminal through a second control switch. The second control switch switches on and off an electrical connection between the sampling capacitor and the intermediate point between the integral capacitor and first input terminal, and plural feedbacks of the quantization results are performed per one sampling cycle.

Abstract: A D/A conversion circuit includes: an output terminal connected to an operational amplifier connected to a quantization circuit; a DAC capacitor; a selection switch switching among reference, first and second voltages to apply to the DAC capacitor as an analog potential; a ground switch connecting the DAC capacitor to a ground; and an output switch connecting the DAC capacitor to the output terminal. In a first period, the selection switch selects one of the reference, first and second voltages according to a quantization result value from the quantization circuit, and connects the one to the DAC capacitor, and the ground switch turns on to charge the DAC capacitor. In a second period, the selection switch selects another one of the first and second voltages, and connects the another one to the DAC capacitor, and the output switch turns on to output the analog potential to the output terminal.

Abstract: An input signal Vin is sampled, when a first terminal of a sampling capacitor is connected to a node and a second terminal of the sampling capacitor is connected to an analog ground. A charge transfer operation is performed, when the first terminal of the sampling capacitor is connected to the analog ground and the second terminal of the sampling capacitor is connected to an inverting input terminal of an operational amplifier. A quantization is performed, when an output of the operational amplifier is input to a quantizer. Most significant bits are generated by repeating a subtraction operation in which a charge subtraction unit subtracts a charge accumulated in the integration capacitor based on a quantization result a predetermined number of times. Least significant bits are generated when a voltage provided by amplifying a voltage corresponding to a charge remaining in the integration capacitor is input to a sub-A/D converter after generation of the most significant bits.

Abstract: A ?? modulator includes an input circuit having a sampling capacitor, an integration circuit, a quantizer and a D/A converter having a DAC capacitor. The input circuit takes in an analog input voltage in the sampling capacitor in a sampling period, and transfers a charge to the integration circuit in a holding period. The D/A converter takes in an analog potential, to which selection switches are connected in the sampling period based on a digital output of the quantizer, in the DAC capacitor, and subtracts a charge from the integration circuit in the holding period. At this time, since the input circuit and the D/A converter are set so that the holding periods do not overlap with each other, an error caused by the lowering of a feedback factor is suppressed.

Abstract: A D/A conversion circuit includes: an output terminal connected to an operational amplifier connected to a quantization circuit; a DAC capacitor; a selection switch switching among reference, first and second voltages to apply to the DAC capacitor as an analog potential; a ground switch connecting the DAC capacitor to a ground; and an output switch connecting the DAC capacitor to the output terminal. In a first period, the selection switch selects one of the reference, first and second voltages according to a quantization result value from the quantization circuit, and connects the one to the DAC capacitor, and the ground switch turns on to charge the DAC capacitor. In a second period, the selection switch selects another one of the first and second voltages, and connects the another one to the DAC capacitor, and the output switch turns on to output the analog potential to the output terminal.

Abstract: An A/D converter includes: an integrator circuit executing ?? modulation to an analog signal to be converted; an adder outputting an addition result of at least an output signal of the integrator circuit and a first reference signal as a reference signal of ?? modulation; a quantizer receives an output signal of the integrator circuit, an output signal of the adder, and a second reference signal as a reference signal in cyclic A/D conversion to generate a result of quantization of the output signal of the integrator circuit and the output signal of the adder; and a controller is configured to switch between a ?? modulation mode and a cyclic mode.

Abstract: A ?? modulator includes: an integrator having an operational amplifier and an integral capacitor; a quantizer outputting a quantization result; a D/A converter connected to a first input terminal of the operational amplifier through a first control switch, and subtracting an electric charge based on the quantization result from an electric charge stored in the integral capacitor to perform feedback of the quantization result to the integrator; a control circuit outputting a digital output value; and a sampling capacitor being connected to the first input terminal through a second control switch. The second control switch switches on and off an electrical connection between the sampling capacitor and the intermediate point between the integral capacitor and first input terminal, and plural feedbacks of the quantization results are performed per one sampling cycle.

Abstract: An A/D converter includes an integrator having an operational amplifier, a first feedback capacitor, and a second feedback capacitor, a quantizer outputting a quantization result of an output signal of the operational amplifier, and a D/A converter having a D/A converter capacitor. The D/A converter capacitor has a first terminal connected to an input terminal of the operational amplifier and a second terminal connected to an output terminal of the operational amplifier. The D/A converter performs a subtraction operation by repeating subtraction of charges accumulated in the first and second feedback capacitors based on the quantization result, and performs a cyclic operation by sequentially repeating subtraction and amplification of the charges accumulated in one of the first and second feedback capacitors based on the quantization result.

Abstract: A gyroscope includes a MEMS sensor having a drive signal input terminal, a drive signal output terminal, and a sense signal output terminal. The gyroscope further includes a quadrature demodulator that demodulates a modulated sense signal and offset canceller circuits that cancel a direct current offset component included in an in-phase signal and a quadrature signal of the sense signal. The gyroscope has a quadrature error detector that detects a quadrature error based on the signals input from the offset canceller circuits and outputs an error signal. The gyroscope also has an IQ corrector circuit that receives the in-phase signal and the quadrature signal of the sense signal as inputs, and outputs a phase signal with a phase based on the error signal.

Abstract: An A/D converter includes an integrator having an operational amplifier, a first feedback capacitor, and a second feedback capacitor, a quantizer outputting a quantization result of an output signal of the operational amplifier, and a D/A converter having a D/A converter capacitor. The D/A converter capacitor has a first terminal connected to an input terminal of the operational amplifier and a second terminal connected to an output terminal of the operational amplifier. The D/A converter performs a subtraction operation by repeating subtraction of charges accumulated in the first and second feedback capacitors based on the quantization result, and performs a cyclic operation by sequentially repeating subtraction and amplification of the charges accumulated in one of the first and second feedback capacitors based on the quantization result.

Abstract: An A/D converter includes: an integrator circuit executing ?? modulation to an analog signal to be converted; an adder outputting an addition result of at least an output signal of the integrator circuit and a first reference signal as a reference signal of ?? modulation; a quantizer receives an output signal of the integrator circuit, an output signal of the adder, and a second reference signal as a reference signal in cyclic A/D conversion to generate a result of quantization of the output signal of the integrator circuit and the output signal of the adder; and a controller is configured to switch between a ?? modulation mode and a cyclic mode.

Abstract: An A/D converter is provided with: an integrator that includes an operational amplifier provided with a first input terminal and an output terminal, and an integration capacitor; a quantizer that outputs a quantization result obtained by quantizing an output signal from the operational amplifier; and a DAC that is connected to the first input terminal and determines DAC voltage. The integrator has a feedback switch between the integration capacitor and the output terminal of the operational amplifier. An analog signal as an input signal is inputted between the integration capacitor and the feedback switch. The integration capacitor samples the analog signal. The quantizer performs the quantization based on the output of the operational amplifier. The DAC sequentially subtracts electric charge accumulated in the integration capacitor to thereby change the analog signal to a digital value.

Abstract: An A/D conversion device acquires an inter-terminal signal of one or more battery cells when detecting a voltage across the battery cells. The A/D conversion device acquires a failure diagnosis signal during a failure diagnosis. A control unit causes the A/D conversion device to perform A/D conversion processing in a ?? mode or a hybrid mode, in which acquiring remaining bits of higher bits after subjecting the higher bits to a ?? type A/D conversion processing, when detecting the inter-terminal signal of the battery cells. The control unit causes the A/D conversion device to perform the A/D conversion processing in a cyclic mode or a hybrid mode, when detecting the failure diagnosis signal during the failure diagnosis.

Abstract: A sensor driving device drives a sensor circuit formed of a Wheatstone bridge, which is connected between a main power supply for supplying a power supply potential and a reference power supply for supplying a reference potential lower than the power supply potential and includes at least one gauge resistor varying a resistance value thereof with deformation caused by external force. The sensor driving device includes a first resistor, which is connected in series with the sensor circuit between the main power supply and the sensor circuit, and a second resistor, which is connected between the sensor circuit and the reference power supply. The sensor driving device further includes a temperature output circuit connected in parallel to the sensor circuit relative to the main power supply. The temperature output circuit includes two output terminals, which output a potential difference smaller than a potential difference between one end of a main power supply side and one end of a reference power supply side.

Abstract: An A/D converter is provided with: an integrator that includes an operational amplifier provided with a first input terminal and an output terminal, and an integration capacitor; a quantizer that outputs a quantization result obtained by quantizing an output signal from the operational amplifier; and a DAC that is connected to the first input terminal and determines DAC voltage. The integrator has a feedback switch between the integration capacitor and the output terminal of the operational amplifier. An analog signal as an input signal is inputted between the integration capacitor and the feedback switch. The integration capacitor samples the analog signal. The quantizer performs the quantization based on the output of the operational amplifier. The DAC sequentially subtracts electric charge accumulated in the integration capacitor to thereby change the analog signal to a digital value.

Abstract: An A/D conversion device acquires an inter-terminal signal of one or more battery cells when detecting a voltage across the battery cells. The A/D conversion device acquires a failure diagnosis signal during a failure diagnosis. A control unit causes the A/D conversion device to perform A/D conversion processing in a ?? mode or a hybrid mode, in which acquiring remaining bits of higher bits after subjecting the higher bits to a ?? type A/D conversion processing, when detecting the inter-terminal signal of the battery cells. The control unit causes the A/D conversion device to perform the A/D conversion processing in a cyclic mode or a hybrid mode, when detecting the failure diagnosis signal during the failure diagnosis.

Abstract: First and second p-type transistors are connected in series between an output terminal and a positive power terminal. First and second n-type transistors are connected in series between a node and a negative power terminal. A third p-type transistor is connected between a node and the positive power terminal. Third and fourth n-type transistors are connected in series between the output terminal and a low potential terminal. Fourth and fifth p-type transistors are connected in series between a node and the negative power terminal. A fifth n-type transistor is connected between a node and the negative power terminal. A high potential is outputted without leak current when the first to fifth p-type transistors are turned on and the first to fifth n-type transistors are turned off.

Abstract: First and second p-type transistors are connected in series between an output terminal and a positive power terminal. First and second n-type transistors are connected in series between a node and a negative power terminal. A third p-type transistor is connected between a node and the positive power terminal. Third and fourth n-type transistors are connected in series between the output terminal and a low potential terminal. Fourth and fifth p-type transistors are connected in series between a node and the negative power terminal. A fifth n-type transistor is connected between a node and the negative power terminal. A high potential is outputted without leak current when the first to fifth p-type transistors are turned on and the first to fifth n-type transistors are turned off.

Abstract: A sensor driving device drives a sensor circuit formed of a Wheatstone bridge, which is connected between a main power supply for supplying a power supply potential and a reference power supply for supplying a reference potential lower than the power supply potential and includes at least one gauge resistor varying a resistance value thereof with deformation caused by external force. The sensor driving device includes a first resistor, which is connected in series with the sensor circuit between the main power supply and the sensor circuit, and a second resistor, which is connected between the sensor circuit and the reference power supply. The sensor driving device further includes a temperature output circuit connected in parallel to the sensor circuit relative to the main power supply. The temperature output circuit includes two output terminals, which output a potential difference smaller than a potential difference between one end of a main power supply side and one end of a reference power supply side.

Abstract: A D/A converter is configured to output tri-level potentials from an output terminal. A high potential terminal and the output terminal are connected through a p-type MOS transistor. An intermediate potential terminal and the output terminal are connected through p-type and n-type MOS transistors, which are connected in series and have low threshold voltages. A low potential terminal and the output terminal are connected through an n-type MOS transistor. The p-type MOS transistor and the n-type MOS transistor connected to the intermediate potential terminal have a positive voltage and a negative voltage between gate-source paths in off-states, respectively, and a substrate bias effect and hence remain in the off-state stably.