Patents by Inventor Tomohiro Nishiyama

Tomohiro Nishiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7135770
    Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: November 14, 2006
    Assignee: NEC Corporation
    Inventors: Tomohiro Nishiyama, Masamoto Tago
  • Publication number: 20060151870
    Abstract: The reliabilities of a wiring substrate and a semiconductor apparatus are improved by reducing the internal stress caused by the difference of thermal expansion coefficients between a base substrate and a semiconductor chip. A wiring layer (5) is provided on one surface of a silicon base (3). An electrode as the uppermost layer of the wiring layer (5) is provided with an external bonding bump (7). A through-electrode (4) is formed in the base (3) for electrically connecting the wiring layer (5) and an electrode terminal. The electrode terminal on the chip mounting surface is bonded to an electrode terminal of a semiconductor chip (1) by an internal bonding bump (6). The thermal expansion coefficient of the silicon base (3) is equivalent to that of the semiconductor chip (1) and not more than that of the wiring layer (5).
    Type: Application
    Filed: November 21, 2003
    Publication date: July 13, 2006
    Applicant: NEC Corporation
    Inventors: Tomohiro Nishiyama, Masamoto Tago
  • Publication number: 20060065978
    Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.
    Type: Application
    Filed: November 14, 2005
    Publication date: March 30, 2006
    Inventors: Tomohiro Nishiyama, Masamoto Tago
  • Publication number: 20050279812
    Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.
    Type: Application
    Filed: June 6, 2005
    Publication date: December 22, 2005
    Inventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
  • Patent number: 6969915
    Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: November 29, 2005
    Assignee: NEC Corporation
    Inventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
  • Publication number: 20040187659
    Abstract: This invention provides a method of cutting a glass substrate to form a plurality of flat panel displays. The method includes forming a scribe line or a line of weakness on a surface of a mother material; treating the mother material with chemical to further weaken the mother material; and cutting the mother material. The scribe line may be formed using a masking technique. The mother material may be treated with chemical by putting the mother material into a chemical solution. Alternatively, the chemical may be sprayed, blown, or exposed to the mother material. The cutting of the mother material may be done by applying mechanical and/or thermal stress along the scribe line.
    Type: Application
    Filed: March 4, 2004
    Publication date: September 30, 2004
    Inventor: Tomohiro Nishiyama
  • Publication number: 20030179592
    Abstract: The object of the present invention is to provide a DC/DC converter and a method for controlling the DC/DC converter whereby losses under light loads are reduced.
    Type: Application
    Filed: October 3, 2002
    Publication date: September 25, 2003
    Applicant: YOKOGAWA ELECTRIC CORPORATION
    Inventors: Tomohiro Nishiyama, Yoshinao Naitou, Kouji Takada, Masuo Hanawaka, Seiichi Noguchi
  • Publication number: 20030151140
    Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.
    Type: Application
    Filed: February 6, 2003
    Publication date: August 14, 2003
    Applicant: NEC CORPORATION
    Inventors: Tomohiro Nishiyama, Masamoto Tago
  • Patent number: 6466462
    Abstract: A DC/DC converter having a control circuit to reduce losses at light load, wherein a first control device turns ON and OFF power to the primary winding of the transformer of the DC/DC converter according to the difference between the output voltage of the DC/DC converter and the desired output voltage, and a second control device turns ON a switching device of a clamping circuit connected to the primary winding for a desired length of time after the first control device turns OFF the power to the primary winding.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: October 15, 2002
    Assignee: Yokogawa Electric Corporation
    Inventors: Tomohiro Nishiyama, Yoshinao Naito, Koji Takada, Masuo Hanawaka
  • Publication number: 20020093096
    Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead flee solder is thinly formed on a UBM layer The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.
    Type: Application
    Filed: January 14, 2002
    Publication date: July 18, 2002
    Applicant: NEC CORPORATION
    Inventors: Masamoto Tago, Tomohiro Nishiyama, Tetuya Tao, Kaoru Mikagi
  • Publication number: 20020067624
    Abstract: The present invention provides a DC/DC converter and a control method thereof whereby losses at a light load are reduced.
    Type: Application
    Filed: October 30, 2001
    Publication date: June 6, 2002
    Inventors: Tomohiro Nishiyama, Yoshinao Naito, Koji Takada, Masuo Hanawaka
  • Publication number: 20010025874
    Abstract: Solder balls are mounted on electrodes with an active resin therebetween. The solder is heated and melts to be connected to pads of an LSI chip, thereby forming solder bumps on the chip. In a method of forming bumps, a method of mounting flip chips, and a mounting structure, by the use of the active resin, a flux washing process can be eliminated and at the same time, an assembly cost can be minimized.
    Type: Application
    Filed: March 27, 2001
    Publication date: October 4, 2001
    Applicant: NEC Corporation
    Inventor: Tomohiro Nishiyama