Patents by Inventor Tomohiro Yamashita

Tomohiro Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060102047
    Abstract: There is provided ink jet ink containing at least a coloring material, in which: the coloring material is a compound represented by the following general formula (I) or a salt thereof; a content (weight %) of the coloring material is 3.0 weight % or more with respect to a total weight of the ink jet ink; in a dispersion distance distribution, measured by a small-angle X-ray scattering method, of molecular aggregates in the ink jet ink whose coloring material concentration is adjusted to 3.0 weight %, a dispersion distance d75 value corresponding to 75% of the distribution is 3.0 mass % is 6.50 nm or more and 7.
    Type: Application
    Filed: December 30, 2005
    Publication date: May 18, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Jun Yoshizawa, Shin-ichi Sato, Kunihiko Nakamura, Daiji Okamura, Tomohiro Yamashita, Masanori Jinnou
  • Publication number: 20060102046
    Abstract: An ink jet ink is disclosed which includes water, a water-soluble organic solvent and a coloring material and has excellent properties. The coloring material is a specific phthalocyanine derivative and is contained in a specific amount in the ink. The water-soluble organic solvent includes a specific amount of 2-pyrrolidone. In addition, a d75 value is in a specific range where the d75 value corresponds to 75% of a dispersion distance distribution, measured by a small angle X-ray scattering method, of molecular aggregates in the ink jet ink whose coloring material concentration is adjusted to 0.5 mass %.
    Type: Application
    Filed: December 30, 2005
    Publication date: May 18, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Daiji Okamura, Shin-ichi Sato, Jun Yoshizawa, Kunihiko Nakamura, Tomohiro Yamashita, Masanori Jinnou
  • Patent number: 7017724
    Abstract: A clutch assembly for starting a vehicle without using a torque converter has a simple structure yet providing high reliability. In the clutch assembly, a clutch and a damper device are housed in a housing connected to a crank shaft of an engine. A boss serving as an output member is connected to an input shaft of an automatic transmission. An output of the engine is connected/disconnected to/from the input shaft upon engagement/disengagement of the clutch. The clutch includes a friction member and a piston fit oil tightly with the housing so as to apply pressure to the friction member. One end of the damper device is connected to a clutch hub, and the other end is connected to the output member. The clutch and the damper device are aligned on the axis of the housing.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: March 28, 2006
    Assignees: Aisin AW Co., LTD, Aisin AW Industries Co., LTD
    Inventors: Masahiro Hayabuchi, Kouji Maeda, Tomohiro Yamashita, Masahiro Yamaguchi, Yoshito Takeshita, Katsunori Tanaka, Yukihiro Fukuda
  • Publication number: 20060039088
    Abstract: A magnetic head contains a write magnetic head and a read magnetic head. The write magnetic head includes a lower core layer, an upper core layer arranged over the lower core layer, and a coil layer for applying a magnetic field to the lower and upper core layers. The read magnetic head includes an upper shield layer, a lower shield layer, and a reproducing device arranged between the upper shield layer and the lower shield layer. The upper shield layer has a dimension A in a direction of track width and a dimension B in a direction of height and has an aspect ratio B/A ranging from 0.6 to 1.2. The dimension A ranges from 75 ?m to 150 ?m.
    Type: Application
    Filed: August 15, 2005
    Publication date: February 23, 2006
    Inventors: Tomohiro Yamashita, Akira Takahashi, Shuji Yanagi
  • Publication number: 20060028775
    Abstract: A magnetic detecting element, which can suppress change in output asymmetry even if the magnetization direction of a pinned magnetic layer is changed 180°, is provided. The magnetic-film-thickness of a second free magnetic layer is increased so as to be greater than that of a first free magnetic layer and offset the torque applied to the second free magnetic layer with that applied to the first free magnetic layer when the sensing current magnetic field occurs. Thus, change in the magnetization direction of the free magnetic layer before and after a sensing current is applied in the magnetic detecting element can be suppressed. The orthogonal state between the free magnetic layer and the pinned magnetic layer is maintained even when a sensing current in the same direction as that before the occurrence is applied in the magnetic detecting element wherein pin inversion occurred, and the output asymmetry is maintained suitably.
    Type: Application
    Filed: July 28, 2005
    Publication date: February 9, 2006
    Inventors: Tomohiro Yamashita, Naoya Hasegawa, Eiji Umetsu, Ryo Nakabayashi, Akira Takahashi
  • Patent number: 6921947
    Abstract: A semiconductor device and a manufacturing method therefor reduce the occurrence of variation in threshold voltage of a MOS transistor formed by a dual oxide process, thereby to improve manufacturing yield. On the main surface of a semiconductor substrate (1), gate oxide films (GX1, GX2) of different thickness are located in active regions (3A, 3B), respectively, and gate electrodes (GT1, GT2) are located on top of the gate oxide films (GX1, GX2), respectively. An isolation insulating film (2) which defines the active region (3A) in a thick-film portion (AR) has an excessively removed edge portion on the side of a MOS transistor (100) and thereby a recessed portion (DP) is formed in the edge portion of the active region (3A). On the other hand, an edge portion of the isolation insulating film (2) in a thin-film portion (BR) on the side of a MOS transistor (200) is not excessively removed.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: July 26, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Haruo Furuta, Tomohiro Yamashita
  • Patent number: 6864545
    Abstract: A plurality of N-type first impurity layers (111) are provided that form stripes in a main surface (110S) of a P-type semiconductor substrate (110). At least one N-type second impurity layer (112) overlaps (or touches) one of the first impurity layers (111). A plurality of gate electrodes are provided on a gate insulating film (121). A plurality of gate electrodes form stripes crossing the first impurity layers (111). A plurality of low-resistance wires (140) are provided on an interlayer insulating film (122). The plurality of low-resistance wires (140) form stripes extending in the same direction as that of the first impurity layers (111). An end (123T2) of each contact plug (123) is entirely in contact with the second impurity layer 112, and does not touch a P-type region of the semiconductor substrate (110).
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: March 8, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Tomohiro Yamashita
  • Patent number: 6835988
    Abstract: A semiconductor device includes an element isolating insulation film having different depths depending on locations where it is formed. A plurality of channel cut layers are formed in one active region in a direction of depth.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: December 28, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Tomohiro Yamashita
  • Patent number: 6777758
    Abstract: P wells (11, 12) having different impurity profiles are adjacently formed in a surface (50S) of a semiconductor substrate (50). A P-type layer (20) having lower resistivity than the P wells (11, 12) is formed in the surface (50S) across the P wells (11, 12), so that the P wells (11, 12) are electrically connected with each other through the P-type layer (20). Contacts (31, 32) fill in contact holes (70H1, 70H2) formed in an interlayer isolation film (70) respectively in contact with the P-type layer (20). The contacts (31, 32) are connected to a wire (40). The wire (70) is connected to a prescribed potential, thereby fixing the P wells (11, 12) to prescribed potentials through the contacts (31, 32) and the P-type layer (20). Thus, the potentials of the wells can be stably fixed and the layout area of elements for fixing the aforementioned potentials can be reduced.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: August 17, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Tomohiro Yamashita, Yoshinori Okumura, Katsuyuki Horita
  • Publication number: 20040124491
    Abstract: A high impurity concentration region (31) that an impurity concentration is higher than that of a center part of a channel region (24) is placed in parts which intersect a Y direction in a side surface (14T) of an active region (14). Furthermore, a low impurity concentration region (32) that an impurity concentration is lower than that of the high impurity concentration region (31) is placed in parts which intersect an X direction in the side surface (14T). A source/drain region (231) overlaps with the low impurity concentration region (32), and in that overlapped part, the formation of a high concentration PN junction is suppressed.
    Type: Application
    Filed: June 3, 2003
    Publication date: July 1, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Tomohiro Yamashita, Katsuyuki Horita, Takashi Kuroi
  • Patent number: 6744113
    Abstract: In a trench (2), an oxynitride film (31ON1) and a silicon oxide film (31O1) are positioned between a doped silicon oxide film (31D) and a substrate (1), and a silicon oxide film (31O2) is positioned closer to the entrance of the trench (2) than the doped silicon oxide film (31D). The oxynitride film (31ON1) is formed by a nitridation process utilizing the silicon oxide film (31O1). The vicinity of the entrance of the trench (2) is occupied by the silicon oxide films (31O1, 31O2) and the oxynitride film (31ON1).
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: June 1, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Kuroi, Tomohiro Yamashita, Katsuyuki Horita
  • Patent number: 6734523
    Abstract: A semiconductor device including a well divided into a plurality of parts by a trench, to effect a reduction in layout area, and a manufacturing method thereof. In the semiconductor device, an element isolation film is formed such as to have to a depth from the main surface of a semiconductor substrate, and the area from the main surface of the substrate to the depth is divided into a plurality of first regions. A first well is formed in each of the first regions. A second well is formed in a second region deeper than the first well in the substrate, and the second well is in contact with some of the first wells.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: May 11, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Shuuichi Ueno, Tomohiro Yamashita, Hidekazu Oda
  • Publication number: 20040053458
    Abstract: In a trench (2), an oxynitride film (31ON1) and a silicon oxide film (31O1) are positioned between a doped silicon oxide film (31D) and a substrate (1), and a silicon oxide film (31O2) is positioned closer to the entrance of the trench (2) than the doped silicon oxide film (31D). The oxynitride film (31ON1) is formed by a nitridation process utilizing the silicon oxide film (31O1). The vicinity of the entrance of the trench (2) is occupied by the silicon oxide films (31O1, 31O2) and the oxynitride film (31ON1).
    Type: Application
    Filed: March 4, 2003
    Publication date: March 18, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Takashi Kuroi, Tomohiro Yamashita, Katsuyuki Horita
  • Publication number: 20040050647
    Abstract: A clutch assembly for starting a vehicle without using a torque converter has a simple structure yet providing high reliability. In the clutch assembly (11, 12, 13), a clutch (10) and a damper device (121, 122) are housed in a housing (2) connected to a crank shaft of an engine. A boss (30) serving as an output member is connected to an input shaft (28) of an automatic transmission. An output of the engine is connected/disconnected to/from the input shaft (28) upon engagement/disengagement of the clutch (10). The clutch (10) includes a friction member (14) and a piston (20) fit oil tightly with the housing (2) so as to apply pressure to the friction member (14). One end of the damper device (121, 122) is connected to a clutch hub (16), and the other end is connected to the output member (30). The clutch (10) and the damper device (121, 122) are aligned on the axis of the housing (2).
    Type: Application
    Filed: September 10, 2003
    Publication date: March 18, 2004
    Inventors: Masahiro Hayabuchi, Kouji Maeda, Tomohiro Yamashita, Masahiro Yamaguchi, Yoshito Takeshita, Katsunori Tanaka, Yukihiro Fukuda
  • Patent number: 6667221
    Abstract: A technique for preventing a decrease in alignment accuracy during a photolithography process is provided. A substrate (1) is prepared, in the surface (80) of which trenches (7) for use as alignment marks and trenches (17, 27) each forming an element isolation structure are formed and on the surface (80) of which a polysilicon film (3) is formed, avoiding the trenches (7, 17, 27). The trenches (7, 17, 27) are filled with an insulation film (30). The insulation film (30) is then selectively etched to partially remove the insulation film (30) in the trenches (7) and to leave the insulation film (30) on side and bottom surfaces (81, 82) of the trenches (7). Using the insulation film (30) in the trenches (7) as a protective film, the polysilicon film (3) is selectively etched. The use of the insulation film (30) in the trenches (7) as a protective film prevents the substrate (1) from being etched and thereby prevents the shape of the trenches (7) from being changed.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: December 23, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masashi Kitazawa, Tomohiro Yamashita, Takashi Kuroi
  • Patent number: 6664602
    Abstract: An object of the invention is to suppress degradation of the effective isolation width between a well and a diffusion layer caused by impurity ion implantation for forming the well performed at a predetermined incident angle. A well is formed by performing impurity ion implantation twice: first impurity ion implantation from a first direction at predetermined incident angle, acceleration voltage and dose; and second impurity ion implantation from a second direction different from the first direction by 180 degrees in a plan view at the same incident angle, acceleration voltage and dose as those in the first impurity ion implantation.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: December 16, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomohiro Yamashita, Masashi Kitazawa
  • Publication number: 20030189233
    Abstract: A plurality of N-type first impurity layers (111) are provided that form stripes in a main surface (110S) of a P-type semiconductor substrate (110). At least one N-type second impurity layer (112) overlaps (or touches) one of the first impurity layers (111). A plurality of gate electrodes are provided on a gate insulating film (121). A plurality of gate electrodes form stripes crossing the first impurity layers (111). A plurality of low-resistance wires (140) are provided on an interlayer insulating film (122). The plurality of low-resistance wires (140) form stripes extending in the same direction as that of the first impurity layers (111). An end (123T2) of each contact plug (123) is entirely in contact with the second impurity layer 112, and does not touch a P-type region of the semiconductor substrate (110).
    Type: Application
    Filed: October 2, 2002
    Publication date: October 9, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Tomohiro Yamashita
  • Publication number: 20030157755
    Abstract: A technique for preventing a decrease in alignment accuracy during a photolithography process is provided. A substrate (1) is prepared, in the surface (80) of which trenches (7) for use as alignment marks and trenches (17, 27) each forming an element isolation structure are formed and on the surface (80) of which a polysilicon film (3) is formed, avoiding the trenches (7, 17, 27). The trenches (7, 17, 27) are filled with an insulation film (30). The insulation film (30) is then selectively etched to partially remove the insulation film (30) in the trenches (7) and to leave the insulation film (30) on side and bottom surfaces (81, 82) of the trenches (7). Using the insulation film (30) in the trenches (7) as a protective film, the polysilicon film (3) is selectively etched. The use of the insulation film (30) in the trenches (7) as a protective film prevents the substrate (1) from being etched and thereby prevents the shape of the trenches (7) from being changed.
    Type: Application
    Filed: August 6, 2002
    Publication date: August 21, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Masashi Kitazawa, Tomohiro Yamashita, Takashi Kuroi
  • Patent number: 6600180
    Abstract: A semiconductor device suppressing increase of the number of types of exposure mask for implantations, preventing complication of manufacturing steps and suppressing the manufacturing cost and manufacturing steps therefor are provided. An impurity implantation region (R81) is formed by first implantation with an exposure mask for implantation having an opening at the lower right and this exposure mask for implantation is turned over for forming another impurity implantation region (R82) by second implantation, thereby forming three types of impurity implantation regions including the impurity implantation region (R81) formed through the first implantation, the impurity implantation region (R82) formed through the second implantation and still another impurity implantation region (R83) formed through the first implantation and the second implantation. Four types of regions inclusive of a region (R84) not subjected to impurity implantation can be formed with a single type of exposure mask for implantation.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: July 29, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Syuuichi Ueno, Tomohiro Yamashita, Hirokazu Sayama
  • Patent number: 6568180
    Abstract: A torque converter including a one-way clutch for supporting a stator radially on a fixed member in such a manner that the stator is rotatable in one direction, and a pair of thrust bearings for supporting the stator axially between a pump impeller and a turbine runner, wherein the diameters of the one-way clutch and both of the thrust bearings are different, and the thrust bearings do not axially overlap at least side bearings of the one-way clutch. With this arrangement, thrust force is not applied to the side bearings, and thus, the side bearings are thinner than conventional side bearings. Accordingly, the area radially inside of the stator in the torque converter is axially shortened.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: May 27, 2003
    Assignee: Aisin Aw Co., Ltd.
    Inventors: Koji Maeda, Tomohiro Yamashita