Patents by Inventor Tomohiro Yoshihara
Tomohiro Yoshihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11334508Abstract: An object of the present invention is to properly secure the consistency of data while suppressing a processing load of a controller on a processor. A storage system includes a plurality of controllers and an HCA that can directly access a memory and can communicate with the controllers. The controller includes a CPU, and a memory having a buffer region into which data is temporarily stored and a cache region into which data is cached. In the case where new data according to a write request is stored into the buffer region, the CPU of the controller sequentially transfers the new data to the cache regions using the HCA without passing through the other buffer regions.Type: GrantFiled: February 8, 2021Date of Patent: May 17, 2022Assignee: Hitachi, Ltd.Inventors: Yuto Kamo, Ryosuke Tatsumi, Tomohiro Yoshihara, Takashi Nagao
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Patent number: 11327660Abstract: A storage system having high reliability and IO processing performance is realized. The storage system includes: a first arithmetic unit configured to receive an input and output request and perform data input and output processing; a first memory connected to the first arithmetic unit; a plurality of storage drives configured to store data; a second arithmetic unit; and a second memory connected to the second arithmetic unit. The first arithmetic unit instructs the storage drive to read data, the storage drive reads the data and stores the data in the second memory, the second arithmetic unit stores the data stored in the second memory in the first memory, and the first arithmetic unit transmits the data stored in the first memory to a request source of a read request for the data.Type: GrantFiled: August 18, 2020Date of Patent: May 10, 2022Assignee: HITACHI, LTD.Inventors: Takashi Nagao, Yuusaku Kiyota, Hideaki Monji, Tomohiro Yoshihara
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Publication number: 20220121402Abstract: The present invention realizes a storage device that has a high data reduction effect without decreasing I/O performances. The storage device includes a processor, an accelerator, a memory, and a storage medium, the processor specifies data to be compressed that is data stored in the storage medium from data stored in the memory and transmits a compression instruction including information relating to the data to be compressed to the accelerator, and the accelerator reads the plurality of continuous items of data from the memory and compresses the plurality of items of data to be compressed obtained by excluding data that is not to be compressed from the plurality of items of data, based on the information relating to the data to be compressed received from the processor, to generate compressed data stored in the storage device.Type: ApplicationFiled: December 24, 2021Publication date: April 21, 2022Inventors: Takashi NAGAO, Tomohiro YOSHIHARA, Akira YAMAMOTO, Yuusaku KIYOTA
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Patent number: 11287977Abstract: Provided is a storage system including a plurality of controllers. The storage system adopts a write-once data storage system and can implement high Input/Output (I/O) processing performance while ensuring data consistency when a failure occurs. Before metadata duplication, recovery data including information necessary for performing roll forward or roll back is stored in each controller, and then the metadata duplication is performed. A recovery data storage processing and the metadata duplication are offloaded to a hardware accelerator.Type: GrantFiled: September 9, 2021Date of Patent: March 29, 2022Assignee: HITACHI, LTD.Inventors: Kenichi Betsuno, Takashi Nagao, Yuusaku Kiyota, Tomohiro Yoshihara
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Patent number: 11226769Abstract: In a large-scale storage system configured by combining a plurality of storage modules, it is possible to improve a read performance for deduplicated data. A large-scale storage system includes a first storage module and a second storage module each connected to a computing machine, the first storage module and the second storage module being connected to each other by a network, the first controller determines whether second data that is same as first data requested to be written is already stored in the second storage module when the first storage module receives a write request from the computing machine, and the first controller determines whether to store the first data in the first storage medium or to refer to the second data in the second storage module in a case in which the second data is already stored in the second storage module.Type: GrantFiled: August 27, 2019Date of Patent: January 18, 2022Assignee: HITACHI, LTD.Inventors: Nobumitsu Takaoka, Tomohiro Yoshihara, Naoya Okada
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Patent number: 11221790Abstract: A plurality of storage drives, for managing data. includes: transmitting a first data update command which specifies a first address, and first new data to a first storage drive included in the plurality of storage drives; updating a sequence number of the first address managed in the first storage drive in response to the first data update command; transmitting a first redundant data update command which specifies a second address of old redundant data, data for updating the old redundant data, and the updated sequence number, to a second storage drive which stores the old redundant data associated with the first address and which is included in the plurality of storage drives; updating the old redundant data based on the data for updating the old redundant data; and updating a sequence number of the second address managed in the second storage drive according to the updated sequence number.Type: GrantFiled: May 24, 2017Date of Patent: January 11, 2022Assignee: HITACHI LTD.Inventor: Tomohiro Yoshihara
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Patent number: 11210032Abstract: The present invention realizes a storage device that has a high data reduction effect without decreasing I/O performances. The storage device includes a processor, an accelerator, a memory, and a storage medium, the processor specifies data to be compressed that is data stored in the storage medium from data stored in the memory and transmits a compression instruction including information relating to the data to be compressed to the accelerator, and the accelerator reads the plurality of continuous items of data from the memory and compresses the plurality of items of data to be compressed obtained by excluding data that is not to be compressed from the plurality of items of data, based on the information relating to the data to be compressed received from the processor, to generate compressed data stored in the storage device.Type: GrantFiled: March 2, 2021Date of Patent: December 28, 2021Assignee: HITACHI, LTD.Inventors: Takashi Nagao, Tomohiro Yoshihara, Akira Yamamoto, Yuusaku Kiyota
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Patent number: 11200172Abstract: A storage system includes a plurality of controllers and a plurality of storage drives. A first cache area and a second cache area are set in a memory. The first cache area is permitted to be written data by the plurality of storage drives, and the second cache area is not permitted to be written data by the plurality of storage drives. In a case where the plurality of controllers duplicates data stored in the cache area to a cache area of another controller for redundancy, the plurality of controllers causes the data to be redundant in a second cache area of the other controller in a case where the data is stored in the first cache area, and causes the data to be redundant in a first cache area of the other controller in a case where the data is stored in the second cache area.Type: GrantFiled: September 12, 2019Date of Patent: December 14, 2021Assignee: HITACHI, LTD.Inventors: Naoya Okada, Tomohiro Yoshihara, Takashi Nagao, Ryosuke Tatsumi
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Publication number: 20210311664Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.Type: ApplicationFiled: February 10, 2021Publication date: October 7, 2021Inventors: Masahiro TSURUYA, Nagamasa MIZUSHIMA, Tomohiro YOSHIHARA, Kentaro SHIMADA
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Publication number: 20210286547Abstract: A plurality of storage drives, for managing data, includes: transmitting a first data update command which specifies a first address, and first new data to a first storage drive included in the plurality of storage drives; updating a sequence number of the first address managed in the first storage drive in response to the first data update command; transmitting a first redundant data update command which specifies a second address of old redundant data, data for updating the old redundant data, and the updated sequence number, to a second storage drive which stores the old redundant data associated with the first address and which is included in the plurality of storage drives; updating the old redundant data based on the data for updating the old redundant data; and updating a sequence number of the second address managed in the second storage drive according to the updated sequence number.Type: ApplicationFiled: May 24, 2017Publication date: September 16, 2021Applicant: HITACHI, LTD.Inventor: Tomohiro YOSHIHARA
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Patent number: 11093134Abstract: To combine and apply a data volume reduction technique and an automatic tier management function, the invention provides a storage system that includes a processor and a storage medium and manages and stores data in tiers. The storage system includes a first storage tier that includes a storage area for storing data, and a second storage tier that includes a storage area for storing the data which is stored in the storage area of the first storage tier and whose storage area is changed. The processor calculates an I/O volume of the data in the first storage tier, determines the tier where data is stored based on the I/O volume, and physically stores data which is stored in the second storage tier in a storage medium corresponding to the determined tier.Type: GrantFiled: September 4, 2019Date of Patent: August 17, 2021Assignee: HITACHI, LTD.Inventors: Kazuki Matsugami, Tomohiro Yoshihara, Ryosuke Tatsumi
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Publication number: 20210247911Abstract: A storage system having high reliability and IO processing performance is realized. The storage system includes: a first arithmetic unit configured to receive an input and output request and perform data input and output processing; a first memory connected to the first arithmetic unit; a plurality of storage drives configured to store data; a second arithmetic unit; and a second memory connected to the second arithmetic unit. The first arithmetic unit instructs the storage drive to read data, the storage drive reads the data and stores the data in the second memory, the second arithmetic unit stores the data stored in the second memory in the first memory, and the first arithmetic unit transmits the data stored in the first memory to a request source of a read request for the data.Type: ApplicationFiled: August 18, 2020Publication date: August 12, 2021Inventors: Takashi Nagao, Yuusaku Kiyota, Hideaki Monji, Tomohiro Yoshihara
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Patent number: 11086562Abstract: In a case where updated data using a first logical address as a write destination and existing data using a second logical address as a write destination duplicate with each other, a computer system writes predetermined data instead of updated data to a memory segment associated with a first physical address, and dynamically maps the first logical address to a second physical address. The computer system transmits a write command of the predetermined data or an unmapping command that designates a virtual address that complies with the first physical address, to a storage device that corresponds to the first physical address. The first and second logical addresses are logical addresses that belong to a logical address range which is at least a part of a logical address space. The first physical address is a physical address that belongs to a physical address range which is at least a part of a physical address space, and is a physical address statically mapped to the first logical address.Type: GrantFiled: September 13, 2016Date of Patent: August 10, 2021Assignee: Hitachi, Ltd.Inventors: Ryosuke Tatsumi, Tomohiro Yoshihara
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Publication number: 20210200473Abstract: The storage system includes a controller and a storage drive accessible from the controller. The controller includes a memory and a processing unit. The memory includes a first cache area in which the writing of data by the storage drive is permitted, and a second cache area in which the writing of data by the storage drive is prohibited. A In the first cache area, the storage of data, by staging-in-advance in response to a read request for a sequential read, by the processing unit is permitted, and the storage of cache data in a dirty state by the processing unit is prohibited. In the second cache area, the storage of the cache data in the dirty state by the processing unit is permitted.Type: ApplicationFiled: September 16, 2020Publication date: July 1, 2021Applicant: Hitachi, Ltd.Inventors: Naoya Okada, Tomohiro Yoshihara, Sadahiro Sugimoto, Takashi Ochi, Jun Miyashita, Toshiya Seki
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Publication number: 20210191658Abstract: Provided is a storage system in which a compression rate of randomly written data can be increased and access performance can be improved. A storage controller 22A includes a cache area 203A configured to store data to be read out of or written into a drive 29. The controller 22A groups a plurality of pieces of data stored in the cache area 203A and input into the drive 29 based on a similarity degree among the pieces of data, selects a group, compresses data of the selected group in group units, and stores the compressed data in the drive 29.Type: ApplicationFiled: August 14, 2020Publication date: June 24, 2021Inventors: Nagamasa MIZUSHIMA, Tomohiro YOSHIHARA, Kentaro SHIMADA
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Publication number: 20210165753Abstract: An object of the present invention is to properly secure the consistency of data while suppressing a processing load of a controller on a processor. A storage system includes a plurality of controllers and an HCA that can directly access a memory and can communicate with the controllers. The controller includes a CPU, and a memory having a buffer region into which data is temporarily stored and a cache region into which data is cached. In the case where new data according to a write request is stored into the buffer region, the CPU of the controller sequentially transfers the new data to the cache regions using the HCA without passing through the other buffer regions.Type: ApplicationFiled: February 8, 2021Publication date: June 3, 2021Inventors: Yuto KAMO, Ryosuke TATSUMI, Tomohiro YOSHIHARA, Takashi NAGAO
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Patent number: 10936518Abstract: An object of the present invention is to properly secure the consistency of data while suppressing a processing load of a controller on a processor. A storage system includes a plurality of controllers and an HCA that can directly access a memory and can communicate with the controllers. The controller includes a CPU, and a memory having a buffer region into which data is temporarily stored and a cache region into which data is cached. In the case where new data according to a write request is stored into the buffer region, the CPU of the controller sequentially transfers the new data to the cache regions using the HCA without passing through the other buffer regions.Type: GrantFiled: August 21, 2019Date of Patent: March 2, 2021Assignee: HITACHI, LTD.Inventors: Yuto Kamo, Ryosuke Tatsumi, Tomohiro Yoshihara, Takashi Nagao
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Patent number: 10853268Abstract: An information processing system including a processor, a memory, and a plurality of drives, wherein when a write request of new data is received, the processor stores the new data in the memory, transmits a response for the write request to a transmission source of the write request, reads old data updated by the new data from a first drive of the plurality of drives and old parity related to the old data from a second drive of the plurality of drives according to transmission of the response, store the old data and the old parity in the memory, generates new parity related to the new data from the new data, the old data, and the old parity stored in the memory, and stores the new data in the first drive to store the new parity in the second drive.Type: GrantFiled: June 15, 2016Date of Patent: December 1, 2020Assignee: HITACHI, LTD.Inventors: Miho Imazaki, Akira Yamamoto, Tomohiro Yoshihara, Kohei Tatara
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Publication number: 20200310975Abstract: A storage system includes a plurality of controllers and a plurality of storage drives. A first cache area and a second cache area are set in a memory. The first cache area is permitted to be written data by the plurality of storage drives, and the second cache area is not permitted to be written data by the plurality of storage drives. In a case where the plurality of controllers duplicates data stored in the cache area to a cache area of another controller for redundancy, the plurality of controllers causes the data to be redundant in a second cache area of the other controller in a case where the data is stored in the first cache area, and causes the data to be redundant in a first cache area of the other controller in a case where the data is stored in the second cache area.Type: ApplicationFiled: September 12, 2019Publication date: October 1, 2020Inventors: Naoya OKADA, Tomohiro YOSHIHARA, Takashi NAGAO, Ryosuke TATSUMI
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Patent number: 10783096Abstract: A storage system provides a logical volume to a computer, manages the logical volume and a port receiving an I/O request for the logical volume in correspondence with each other, and holds assigned processor management information for managing correspondence between a processor for executing I/O processing based on an I/O request accumulated in a queue and an assigned port being a port corresponding to the queue. The processor identifies an assigned port on the basis of the assigned processor management information, executes I/O processing for the logical volume corresponding to the assigned port, and executes I/O processing on the basis of an I/O request received via the assigned port corresponding to another operation core.Type: GrantFiled: August 30, 2018Date of Patent: September 22, 2020Assignee: HITACHI, LTD.Inventors: Takashi Nagao, Tomohiro Yoshihara, Kohei Tatara, Miho Kobayashi