Abstract: The polysilicon resistance has a large resistance variation rate after the end of the mold packaging process. In order to enable high-precision trimming, it is desired to realize a resistance which is hardly affected by stress and temperature fluctuation generated in a substrate by a mold packaging process. A resistance element is formed in a plurality of wiring layers, and has a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and a repeating pattern of an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the interlayer conductive layer is formed of a plurality of types of materials.

Abstract: A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.

Abstract: The polysilicon resistance has a large resistance variation rate after the end of the mold packaging process. In order to enable high-precision trimming, it is desired to realize a resistance which is hardly affected by stress and temperature fluctuation generated in a substrate by a mold packaging process. A resistance element is formed in a plurality of wiring layers, and has a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and a repeating pattern of an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the interlayer conductive layer is formed of a plurality of types of materials.

Abstract: A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.

Abstract: It is possible to flexibly respond to accuracy required for a temperature sensor. An oscillator 11 generates a clock signal. The oscillator 11 is configured to be capable of changing a relationship between a frequency of the clock signal and a temperature. A counter 13 is configured to count the clock signal generated by the oscillator 11 by using a reference signal having a frequency not changing depending on a temperature. A CPU 16 generates temperature information based on the relationship between the frequency of the clock signal and the temperature in the oscillator 11 and a count value of the counter 13. The control circuit 14 changes the relationship between the frequency of the clock signal and the temperature in the oscillator 11 when the counter 13 overflows.

Abstract: A semiconductor device includes: a voltage generation unit that generates a first voltage having a first temperature characteristic; a constant voltage generation unit that generates a constant voltage; and an adjustment unit that generates a second voltage having a second temperature characteristic and a third voltage having a third temperature characteristic using the first voltage and the constant voltage. The constant voltage generation unit generates the constant voltage independently of the adjustment unit. One of the second and third temperature characteristics is an opposite characteristic to the first temperature characteristic. The device can also include a control unit that selects one of the second and third voltages in response to a predetermined setting value.

Abstract: A semiconductor device includes: a voltage generation unit that generates a first voltage having a first temperature characteristic; a constant voltage generation unit that generates a constant voltage; and an adjustment unit that generates a second voltage having a second temperature characteristic and a third voltage having a third temperature characteristic using the first voltage and the constant voltage. The constant voltage generation unit generates the constant voltage independently of the adjustment unit. One of the second and third temperature characteristics is an opposite characteristic to the first temperature characteristic. The device can also include a control unit that selects one of the second and third voltages in response to a predetermined setting value.

Abstract: A constant current generation circuit of the invention includes: a temperature variable voltage generation unit that generates a first variation voltage whose voltage value fluctuates with temperature; a variation gradient adjustment unit that generates a second variation voltage based on a reference voltage smaller in the amount of variation with temperature than the first variation voltage and the first variation voltage; and a current generation unit that includes a current setting resistor whose resistance value fluctuates with temperature and generates an output current based on the second variation voltage and the current setting resistor. The variation gradient adjustment unit sets the coefficient of variation with temperature of the second variation voltage so that the difference between it and the coefficient of variation with temperature of the resistance value of the current setting resistor is within a preset first stipulated range.

Abstract: A semiconductor device includes: a resistance R whose resistance value varies in response to a substrate temperature variation; a resistance corrector that is coupled in series with the resistance R and switches its resistance value by a preset resistance step width to suppress a resistance value variation of the resistance R; a first voltage generator for generating a first voltage that varies in response to the substrate temperature; a second voltage generator for generating second voltages Vf1 to Vfn?1 for specifying the first voltage at a point when a switching operation of the resistance value of the resistance corrector is performed; and a resistance switch unit for switching the resistance value of the resistance corrector by comparing the first voltage and the second voltages Vf1 to Vfn?1.

Abstract: A semiconductor device according to an exemplary aspect of the invention is capable of being selectively switched between an oscillation circuit and a signal input-output circuit, and includes first and second external connecting terminals that are connectable to an oscillation device; an inverting amplifier an input side of which is electrically connected to the first external connecting terminal through a coupling capacitor and an output side of which is electrically connected to the second external connecting terminal; a feedback resistor connected to the input side and the output side of the inverting amplifier; a bias stabilization circuit that stabilizes a bias applied to the coupling capacitor; a first signal input-output portion connected to the first external connecting terminal; and a second signal input-output portion connected to the second external connecting terminal.

Abstract: A method of manufacturing a semiconductor memory device which includes forming a conductive layer for a floating gate above a semiconductor layer intervening a gate insulating film therebetween, then, forming, over the conductive layer, a first spacer comprising a first silicon oxide material and a second spacer adjacent with the first spacer and comprising a second silicon oxide material, the second silicon oxide material having an etching rate lower than that of the first silicon oxide material, selectively removing the conductive layer by using the first and the second spacers as a mask, and removing the first spacer to expose a portion of the conductive layer. Since the etching rate for the second spacer is lower compared with the etching rate for the first spacer, the etching amount of the second spacer caused upon removal of the first spacer can be suppressed and, as a result, the productivity and the reliability of the semiconductor memory device can be improved.

Abstract: A variable-capacitance device includes a first capacitance element coupled between a first power supply terminal and an output terminal, a capacitance selection switch that is turned on and off in accordance with a capacitance switching signal, a second capacitance element coupled in parallel to the first capacitance element and in series to the capacitance selection switch, and an error correction circuit configured to operate such that in a state in which the capacitance selection switch is in an OFF state, in response to a charge reset signal that causes a voltage at the output terminal to be reset to a reset voltage, the error correction circuit substantially eliminates a difference between the voltage at the output terminal and a voltage at a capacitance switching node at which the second capacitance element is coupled to the capacitance selection switch.

Abstract: An oscillator circuit in accordance with an aspect of the present invention includes a filter capacitor that generates an oscillating frequency control voltage according to a charge amount accumulated based on an oscillating frequency setting current, an oscillator that changes a frequency of an oscillation signal to be output according to the oscillating frequency control voltage, a control circuit that generates a timing control signal, a frequency detection circuit that generates a frequency detection voltage based on the timing control signal, a voltage level of the frequency detection voltage being changed according to a length of the period of the oscillation signal, and a differential amplifier that continuously changes the oscillating frequency setting current according to a voltage difference between the frequency detection voltage and a reference voltage, and outputs the resultant oscillating frequency setting current to the filter capacitor.

Abstract: A semiconductor device according to an exemplary aspect of the invention is capable of being selectively switched between an oscillation circuit and a signal input-output circuit, and includes first and second external connecting terminals that are connectable to an oscillation device; an inverting amplifier an input side of which is electrically connected to the first external connecting terminal through a coupling capacitor and an output side of which is electrically connected to the second external connecting terminal; a feedback resistor connected to the input side and the output side of the inverting amplifier; a bias stabilization circuit that stabilizes a bias applied to the coupling capacitor; a first signal input-output portion connected to the first external connecting terminal; and a second signal input-output portion connected to the second external connecting terminal.

Abstract: A constant current generation circuit of the invention includes: a temperature variable voltage generation unit that generates a first variation voltage whose voltage value fluctuates with temperature; a variation gradient adjustment unit that generates a second variation voltage based on a reference voltage smaller in the amount of variation with temperature than the first variation voltage and the first variation voltage; and a current generation unit that includes a current setting resistor whose resistance value fluctuates with temperature and generates an output current based on the second variation voltage and the current setting resistor. The variation gradient adjustment unit sets the coefficient of variation with temperature of the second variation voltage so that the difference between it and the coefficient of variation with temperature of the resistance value of the current setting resistor is within a preset first stipulated range.

Abstract: A semiconductor device according to an exemplary aspect of the invention is capable of being selectively switched between an oscillation circuit and a signal input-output circuit, and includes first and second external connecting terminals that are connectable to an oscillation device; an inverting amplifier an input side of which is electrically connected to the first external connecting terminal through a coupling capacitor and an output side of which is electrically connected to the second external connecting terminal; a feedback resistor connected to the input side and the output side of the inverting amplifier; a bias stabilization circuit that stabilizes a bias applied to the coupling capacitor; a first signal input-output portion connected to the first external connecting terminal; and a second signal input-output portion connected to the second external connecting terminal.

Abstract: A variable-capacitance device includes a first capacitance element coupled between a first power supply terminal and an output terminal, a capacitance selection switch that is turned on and off in accordance with a capacitance switching signal, a second capacitance element coupled in parallel to the first capacitance element and in series to the capacitance selection switch, and an error correction circuit configured to operate such that in a state in which the capacitance selection switch is in an OFF state, in response to a charge reset signal that causes a voltage at the output terminal to be reset to a reset voltage, the error correction circuit substantially eliminates a difference between the voltage at the output terminal and a voltage at a capacitance switching node at which the second capacitance element is coupled to the capacitance selection switch.

Abstract: An oscillator circuit in accordance with an aspect of the present invention includes a filter capacitor that generates an oscillating frequency control voltage according to a charge amount accumulated based on an oscillating frequency setting current, an oscillator that changes a frequency of an oscillation signal to be output according to the oscillating frequency control voltage, a control circuit that generates a timing control signal, a frequency detection circuit that generates a frequency detection voltage based on the timing control signal, a voltage level of the frequency detection voltage being changed according to a length of the period of the oscillation signal, and a differential amplifier that continuously changes the oscillating frequency setting current according to a voltage difference between the frequency detection voltage and a reference voltage, and outputs the resultant oscillating frequency setting current to the filter capacitor.

Abstract: A semiconductor device according to an exemplary aspect of the invention is capable of being selectively switched between an oscillation circuit and a signal input-output circuit, and includes first and second external connecting terminals that are connectable to an oscillation device; an inverting amplifier an input side of which is electrically connected to the first external connecting terminal through a coupling capacitor and an output side of which is electrically connected to the second external connecting terminal; a feedback resistor connected to the input side and the output side of the inverting amplifier; a bias stabilization circuit that stabilizes a bias applied to the coupling capacitor; a first signal input-output portion connected to the first external connecting terminal; and a second signal input-output portion connected to the second external connecting terminal.

Abstract: A method of manufacturing a semiconductor memory device which includes forming a conductive layer for a floating gate above a semiconductor layer intervening a gate insulating film therebetween, then, forming, over the conductive layer, a first spacer comprising a first silicon oxide material and a second spacer adjacent with the first spacer and comprising a second silicon oxide material, the second silicon oxide material having an etching rate lower than that of the first silicon oxide material, selectively removing the conductive layer by using the first and the second spacers as a mask, and removing the first spacer to expose a portion of the conductive layer. Since the etching rate for the second spacer is lower compared with the etching rate for the first spacer, the etching amount of the second spacer caused upon removal of the first spacer can be suppressed and, as a result, the productivity and the reliability of the semiconductor memory device can be improved.