Patents by Inventor Tomoki Ishii

Tomoki Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190242985
    Abstract: An ultrasonic sensor includes an ultrasonic element and an element accommodation case. A side wall portion of the element accommodation case has a tubular shape surrounding a directional central axis. A bottom wall portion and a top wall portion of the element accommodation case cover ends of the side wall portion in a direction along the directional central axis. The top wall portion has a diaphragm portion. The bottom wall portion supports the ultrasonic element. For example, the ultrasonic element is opposed to the diaphragm portion across a gap defining an interval corresponding to an integral multiple of half of a wavelength of ultrasonic vibration. Alternatively, the diaphragm portion is formed of a material having an acoustic impedance of 50×105 Pa·s/m or more and 5000×105 Pa·s/m or less, and has a thickness of 1 mm or less.
    Type: Application
    Filed: January 30, 2019
    Publication date: August 8, 2019
    Inventors: ltaru ISHII, Tomoki TANEMURA, Tatsuya KAMIYA
  • Patent number: 10305825
    Abstract: A bus control device (401a) includes a storage (408) that stores a transmission order of data pieces transmitted from a first node (402) to each second node (403); a sorter (413) that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer (409) that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller (410) that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 28, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Atsushi Yoshida, Tomoki Ishii, Satoru Tokutsu, Takao Yamaguchi, Yuuki Soga
  • Patent number: 10225168
    Abstract: An exemplary interface apparatus includes: a header generator which receives, in a first order, a plurality of request headers extracted from a plurality of request packets, generates response headers associated with the request headers, and then stores the response headers so that the response headers are read in the first order; and a header order controller which controls the header generator so that if the plurality of request data have been transmitted to the memory in a second order, the respective response headers are read in the second order.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: March 5, 2019
    Assignee: Panasonic Intellectual Property Management Co. Ltd
    Inventors: Tomoki Ishii, Takao Yamaguchi, Atsushi Yoshida, Satoru Tokutsu, Yuuki Soga
  • Patent number: 10104006
    Abstract: In the bus system, bus interface apparatuses and routers are connected together through packet exchange buses which have been established on the integrated circuit. The bus interface apparatuses are respectively connected to transmission nodes which transmit data of mutually different numbers of bits in one cycle of operation of the bus system. Each of the bus interface apparatuses generates and transmits a packet based on data received from the transmission node connected and header information including size information indicating the number of bits with respect to the transmission node connected. The router analyzes the packet, gets the size information from the header information, determines how to allocate a space in the buffer for storage by reference to the size information gotten, and stores the received packet in the buffer.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: October 16, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO. LTD
    Inventors: Atsushi Yoshida, Satoru Tokutsu, Tomoki Ishii, Takao Yamaguchi, Yuuki Soga
  • Publication number: 20180198739
    Abstract: A bus control device (401a) includes a storage (408) that stores a transmission order of data pieces transmitted from a first node (402) to each second node (403); a sorter (413) that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer (409) that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller (410) that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Inventors: Atsushi YOSHIDA, Tomoki ISHII, Satoru TOKUTSU, Takao YAMAGUCHI, Yuuki SOGA
  • Patent number: 9961005
    Abstract: A bus system (100) for a semiconductor circuit transmits data on a networked bus between a first node and at least one second node via a relay device (250) arranged on the bus. The bus system (100) includes a first bus of a low delay and a second bus of a high delay. The first node generates a plurality of packets by attaching, to the data stored in a buffer (202), information specifying a priority of transmission. The relay device (250) converts a priority based on a priority conversion rule, which is determined based on a transmission delay of the high-delay bus, allocates a buffer of a destination relay device to which each packet is to be sent, based on the converted priority, and sends packets in a descending order. The relay device (250) stores packets in a buffer (252) based on the priority.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: May 1, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Satoru Tokutsu, Tomoki Ishii, Atsushi Yoshida, Takao Yamaguchi, Nobuyuki Ichiguchi
  • Patent number: 9942174
    Abstract: A bus control device (401a) includes a storage (408) that stores a transmission order of data pieces transmitted from a first node (402) to each second node (403); a sorter (413) that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer (409) that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller (410) that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: April 10, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Atsushi Yoshida, Tomoki Ishii, Satoru Tokutsu, Takao Yamaguchi, Yuuki Soga
  • Patent number: 9798603
    Abstract: A communication device includes: a receiving terminal; a storage device which stores a rule in which a condition regarding a bus system operation environment and an error tolerance scheme are associated with each other, and information regarding a path length; an error processor which determines the error tolerance scheme by utilizing the condition regarding the bus system operation environment and the rule so as to generate error tolerance information corresponding to the received data according to the determined error tolerance scheme; and a sending terminal for sending at least one packet including the error tolerance information and the data to the bus. The operation environment-related condition is a condition for granting an error tolerance for a transmission path of which a bus path length to another communication device, which is a destination of the data, is greater than a predetermined value.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: October 24, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takao Yamaguchi, Atsushi Yoshida, Tomoki Ishii, Satoru Tokutsu
  • Patent number: 9703732
    Abstract: An exemplary interface apparatus according to the present disclosure connects together an initiator and a packet exchange type bus network formed on the integrated circuit. In the bus network, if the initiator has submitted request data with a deadline time specified, the initiator receives, by the deadline time, response data to be issued by a node in response to the request data. The interface apparatus includes: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: July 11, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tomoki Ishii, Takao Yamaguchi, Atsushi Yoshida, Satoru Tokutsu, Nobuyuki Ichiguchi
  • Patent number: 9678905
    Abstract: In a bus control system for a semiconductor circuit, data is transmitted between first and second nodes over a network of buses. The bus controller is connected directly to the first node and includes: a route load detector which detects loads on routes that form at least one of a group of forward routes leading from the first to the second node and a group of backward routes leading from the second to the first node; a candidate route extraction circuit which extracts a candidate route from the group of routes so that loads on the routes that form the group become uniform; a route determining circuit which determines the route to transmit the data based on the candidate route and a predetermined selection rule; and a data communication circuit which transmits the data between the first and second nodes based on header information including route information indicating the route.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: June 13, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tomoki Ishii, Takao Yamaguchi, Atsushi Yoshida, Satoru Tokutsu, Yuuki Soga
  • Patent number: 9606945
    Abstract: The access controller conducts arbitration between first nodes, each of which is attempting to transmit data to any of second nodes as destinations through a network of buses. The access controller includes: a buffer which receives the data that have been provided by the first nodes with mutually different required qualities and destinations, classifies the data according to their destinations and required qualities, and stores the classified data separately; an inter-class arbitrator which sequentially selects one of the required qualities of the data after another in the order of their severity; an inter-destination arbitrator which selects the destinations of the data to be transmitted and gets the transmission quantities of the data distributed among the destinations; and a transmission controller which controls transmission of the data based on the required qualities selected by the inter-class arbitrator and the destinations selected by the inter-destination arbitrator.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: March 28, 2017
    Assignee: Panasonic Intellectuasl Property Management Co., Ltd.
    Inventors: Atsushi Yoshida, Satoru Tokutsu, Tomoki Ishii, Takao Yamaguchi, Nobuyuki Ichiguchi
  • Patent number: 9444740
    Abstract: A router includes a buffer selection section for receiving a flit from an adjacent router and determining whether to store the flit on an input buffer or to store the flit on a bypass buffer. The buffer selection section executes at least one of a first control of, when a bypass process was performed, changing at least one of a transmission path and a transmission flow rate of data based on a transmission state of the router; and a second control of, when a bypass control section did not execute the bypass process, changing at least one of a transmission path and a transmission flow rate of data based on a transmission state of another first router at which data not subjected to the bypass process and data subjected to the bypass process by another second router are joined together.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: September 13, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takao Yamaguchi, Atsushi Yoshida, Tomoki Ishii
  • Patent number: 9436642
    Abstract: An exemplary semiconductor circuit bus system includes: a first bus comprised of distributed buses and having a first transfer rate; a second bus with a second transfer rate higher than the first transfer rate; a transmission node; a bus interface (IF) to connect the transmission node to the first bus; a router which connects the first and second buses; and a reception node connected to the second bus. The bus IF controls the flow rate of data flowing through the transmission routes of the first bus by reference to information about the amounts of transmissible data of the transmission routes. The router allocates the amounts of transmissible data to the transmission routes of the first bus and provides information about the amounts of transmissible data of the transmission routes for the bus IF and also controls the flow rate of the data flowing through the second bus.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: September 6, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takao Yamaguchi, Atsushi Yoshida, Tomoki Ishii, Satoru Tokutsu
  • Patent number: 9426099
    Abstract: An router includes: a plurality of data storage sections configured to store input data; and an arbiter configured to compare the availability of at least one of the plurality of data storage sections with respect to data that is stored in that data storage section and that shares at least a part of a transmission path to the availability of another data storage section in an adjacent router with respect to that data that also shares at least that part of the transmission path, thereby determining, based on a result of the comparison, whether or not to output that data.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: August 23, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Atsushi Yoshida, Takao Yamaguchi, Tomoki Ishii
  • Patent number: 9379983
    Abstract: In a bus system including a bus master, a first bus, and a second bus to connect them together, this router is arranged on the second bus to relay packets. The bus master outputs packets including information about at least one of (N+1) predetermined types of quality requirements. The second bus transmits packets designating at most N types of quality requirements. An exemplary router controls sending of the packets, with respect to at most N types of buffers that classify and store the packets by reference to the quality requirement type information and the packets stored in the buffers, so that the packets are sent in the descending order of their level of the quality requirement. The router controls sending schedule of the traffic flows by sensing a difference between the (N+1) different types of quality requirements.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: June 28, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Atsushi Yoshida, Satoru Tokutsu, Tomoki Ishii, Takao Yamaguchi
  • Patent number: 9294402
    Abstract: A router includes an input section configured to receive data, a buffer section including a plurality of data storage sections and configured to store the data received by the input section, and an output section configured to output the data stored on the buffer section. The router also includes an allocation processing section configured to determine whether or not to store the data on a pre-secured specific data storage section among the plurality of data storage sections, or whether or not to store the data on a pre-secured specific data storage section among a plurality of data storage sections in a buffer section of another router which is an output destination, the determination being made based on information representing burstiness of the data received by the input section.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: March 22, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takao Yamaguchi, Atsushi Yoshida, Tomoki Ishii
  • Patent number: 9270604
    Abstract: In an NoC bus system, data is transmitted between first and second nodes through a router. The data includes performance-ensuring data which guarantees throughput and/or a permitted time delay. The first node generates packets, each including the data to be transmitted and classification information that indicates the class of that data to be determined according to its required performance, and controls transmission of the packets. The router includes a buffer section configured to store the received packets separately after having classified the packets according to their required performance by reference to the classification information, and a relay controller configured to control transmission of the packets stored in the buffer section at a transmission rate which is equal to or higher than the sum of transmission rates to be guaranteed for every first node associated with the classification information by reference to each piece of the classification information.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: February 23, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Satoru Tokutsu, Tomoki Ishii, Atsushi Yoshida, Takao Yamaguchi, Takashi Yamada
  • Patent number: 9262355
    Abstract: A controller as an embodiment of the present disclosure controls a timing of transmitting an access request that has been received from an initiator (or its transmission interval). The controller includes: transmitting and receiving circuitry configured to receive an access request related to burst accesses from a first initiator that is connected via a first bus to, and adjacent to, the transmitting and receiving circuitry and configured to transmit the access request to a second bus implemented as a network; and a transmission interval controller configured to control the timing of transmitting the access request that has been received from the first initiator according to density of the burst accesses during a period in which the burst accesses continue and an access load on the second bus.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: February 16, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tomoki Ishii, Takao Yamaguchi, Atsushi Yoshida
  • Patent number: 9264371
    Abstract: An exemplary router is provided for an integrated circuit that has distributed buses and is arranged on a transmission route that leads from a transmission node to a reception node on the distributed buses to relay data. The distributed buses include first and second routes, each leading from the router to the reception node. The router includes a notifying section which sends a data transfer permission request to a second router on the first route and a third router on the second route and which determines whether or not the request is approved before a predetermined standby period passes to see if there is any abnormality in the first and second routes.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: February 16, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takao Yamaguchi, Atsushi Yoshida, Tomoki Ishii
  • Patent number: 9189013
    Abstract: This controller is used in a system in which initiators and targets are connected via distributed buses to control transmission timing of an access request received from the initiators. The controller stores intermittent information including information about an intermittent period in which interference between packets can be restricted and bus operating frequency information indicating a bus operating frequency at which real-time performance is guaranteed for each initiator and which has been generated based on system configuration information and flow configuration information indicating, on a flow basis, a specification required for each initiator to access the target. The controller includes a clock generator; communications circuitry; and transmission interval setting circuitry which sets a time to send transmission permission responsive to a transmission request based on the intermittent period, a time when the transmission request is detected, and a previous transmission time.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: November 17, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tomoki Ishii, Takao Yamaguchi, Atsushi Yoshida