Patents by Inventor Tomoki Ishii

Tomoki Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150242261
    Abstract: A communication device includes: a receiving terminal; a storage device which stores a rule in which a condition regarding a bus system operation environment and an error tolerance scheme are associated with each other, and information regarding a path length; an error processor which determines the error tolerance scheme by utilizing the condition regarding the bus system operation environment and the rule so as to generate error tolerance information corresponding to the received data according to the determined error tolerance scheme; and a sending terminal for sending at least one packet including the error tolerance information and the data to the bus. The operation environment-related condition is a condition for granting an error tolerance for a transmission path of which a bus path length to another communication device, which is a destination of the data, is greater than a predetermined value.
    Type: Application
    Filed: May 11, 2015
    Publication date: August 27, 2015
    Inventors: Takao YAMAGUCHI, Atsushi YOSHIDA, Tomoki ISHII, Satoru TOKUTSU
  • Patent number: 9094231
    Abstract: The router is used to relay a packet to be transmitted from one node to another in an integrated circuit that has distributed buses according to a packet exchange method. The router includes: a plurality of buffers, each of which configured to store packets with information indicating their transmission node; a classifying section configured to classify the buffers that store the packets into a number of groups according to the transmission nodes of the packets; a selecting section configured to select at least one of the buffers of each group; and an output port configured to sequentially output the packets that are stored in the selected buffer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: July 28, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Atsushi Yoshida, Tomoki Ishii, Takao Yamaguchi
  • Patent number: 9075747
    Abstract: A bus controller is arranged on a plurality of network communication buses that connect together a plurality of bus masters, each sending out a packet, and at least one node, to which the packet is sent from each said bus master, in order to control the transmission route of a packet that is flowing through the plurality of communication buses. The bus controller includes: a route diagram manager configured to manage a plurality of transmission routes and their respective transmission statuses; a parameter generator configured to generate either a parameter that conforms to a predetermined probability distribution or a parameter that follows a predefined rule; a processor configured to select one of the plurality of transmission routes based on the respective transmission statuses of the transmission routes and the parameter; and a relay configured to perform relay processing on the packet that is flowing through the communication bus.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: July 7, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tomoki Ishii, Takao Yamaguchi, Atsushi Yoshida
  • Publication number: 20150180784
    Abstract: A bus system (100) for a semiconductor circuit transmits data on a networked bus between a first node and at least one second node via a relay device (250) arranged on the bus. The bus system (100) includes a first bus of a low delay and a second bus of a high delay. The first node generates a plurality of packets by attaching, to the data stored in a buffer (202), information specifying a priority of transmission. The relay device (250) converts a priority based on a priority conversion rule, which is determined based on a transmission delay of the high-delay bus, allocates a buffer of a destination relay device to which each packet is to be sent, based on the converted priority, and sends packets in a descending order. The relay device (250) stores packets in a buffer (252) based on the priority.
    Type: Application
    Filed: March 6, 2015
    Publication date: June 25, 2015
    Inventors: Satoru TOKUTSU, Tomoki ISHII, Atsushi YOSHIDA, Takao YAMAGUCHI, Nobuyuki ICHIGUCHI
  • Publication number: 20150180805
    Abstract: A bus control device (401a) includes a storage (408) that stores a transmission order of data pieces transmitted from a first node (402) to each second node (403); a sorter (413) that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer (409) that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller (410) that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.
    Type: Application
    Filed: March 6, 2015
    Publication date: June 25, 2015
    Inventors: Atsushi YOSHIDA, Tomoki ISHII, Satoru TOKUTSU, Takao YAMAGUCHI, Yuuki SOGA
  • Patent number: 9025457
    Abstract: Routers in a data transfer system relay data between the first node and each of the second nodes. A router includes a load value processing section and an aggregation decision section. The load value processing section obtains information about a load value of another router connected to a communications bus. The load value is a time delay caused by that another router and/or the throughput of that router. The aggregation decision section chooses one of the second nodes at which the data is to be received, and determines a transmission path between the second node chosen and the first node in accordance with information about the load value obtained from each router and information determined during a design process about the number of stages of routers from the first node through each second node and/or the length of data to be transferred.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: May 5, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takao Yamaguchi, Atsushi Yoshida, Tomoki Ishii
  • Publication number: 20150052283
    Abstract: An exemplary interface apparatus according to the present disclosure connects together an initiator and a packet exchange type bus network formed on the integrated circuit. In the bus network, if the initiator has submitted request data with a deadline time specified, the initiator receives, by the deadline time, response data to be issued by a node in response to the request data. The interface apparatus includes: a correcting circuit which corrects the deadline time of the request data according to the timing when the request data has been submitted, thereby generating corrected deadline time information; a header generator which generates a packet header that stores the corrected deadline time information; and a packetizing processor which generates a request packet based on the request data and the packet header.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 19, 2015
    Inventors: Tomoki ISHII, Takao YAMAGUCHI, Atsushi YOSHIDA, Satoru TOKUTSU, Nobuyuki ICHIGUCHI
  • Publication number: 20150010005
    Abstract: In the bus system, bus interface apparatuses and routers are connected together through packet exchange buses which have been established on the integrated circuit. The bus interface apparatuses are respectively connected to transmission nodes which transmit data of mutually different numbers of bits in one cycle of operation of the bus system. Each of the bus interface apparatuses generates and transmits a packet based on data received from the transmission node connected and header information including size information indicating the number of bits with respect to the transmission node connected. The router analyzes the packet, gets the size information from the header information, determines how to allocate a space in the buffer for storage by reference to the size information gotten, and stores the received packet in the buffer.
    Type: Application
    Filed: September 22, 2014
    Publication date: January 8, 2015
    Inventors: Atsushi YOSHIDA, Satoru TOKUTSU, Tomoki ISHII, Takao YAMAGUCHI, Yuuki SOGA
  • Publication number: 20140365632
    Abstract: An exemplary interface apparatus includes: a header generator which receives, in a first order, a plurality of request headers extracted from a plurality of request packets, generates response headers associated with the request headers, and then stores the response headers so that the response headers are read in the first order; and a header order controller which controls the header generator so that if the plurality of request data have been transmitted to the memory in a second order, the respective response headers are read in the second order.
    Type: Application
    Filed: August 26, 2014
    Publication date: December 11, 2014
    Inventors: Tomoki ISHII, Takao YAMAGUCHI, Atsushi YOSHIDA, Satoru TOKUTSU, Yuuki SOGA
  • Publication number: 20140365703
    Abstract: An exemplary semiconductor circuit bus system includes: a first bus comprised of distributed buses and having a first transfer rate; a second bus with a second transfer rate higher than the first transfer rate; a transmission node; a bus interface (IF) to connect the transmission node to the first bus; a router which connects the first and second buses; and a reception node connected to the second bus. The bus IF controls the flow rate of data flowing through the transmission routes of the first bus by reference to information about the amounts of transmissible data of the transmission routes. The router allocates the amounts of transmissible data to the transmission routes of the first bus and provides information about the amounts of transmissible data of the transmission routes for the bus IF and also controls the flow rate of the data flowing through the second bus.
    Type: Application
    Filed: August 25, 2014
    Publication date: December 11, 2014
    Inventors: Takao YAMAGUCHI, Atsushi YOSHIDA, Tomoki ISHII, Satoru TOKUTSU
  • Publication number: 20140223053
    Abstract: The access controller conducts arbitration between first nodes, each of which is attempting to transmit data to any of second nodes as destinations through a network of buses. The access controller includes: a buffer which receives the data that have been provided by the first nodes with mutually different required qualities and destinations, classifies the data according to their destinations and required qualities, and stores the classified data separately; an inter-class arbitrator which sequentially selects one of the required qualities of the data after another in the order of their severity; an inter-destination arbitrator which selects the destinations of the data to be transmitted and gets the transmission quantities of the data distributed among the destinations; and a transmission controller which controls transmission of the data based on the required qualities selected by the inter-class arbitrator and the destinations selected by the inter-destination arbitrator.
    Type: Application
    Filed: April 7, 2014
    Publication date: August 7, 2014
    Applicant: Panasonic Corporation
    Inventors: Atsushi YOSHIDA, Satoru TOKUTSU, Tomoki ISHII, Takao YAMAGUCHI, Nobuyuki ICHIGUCHI
  • Publication number: 20140204740
    Abstract: In an NoC bus system, data is transmitted between first and second nodes through a router. The data includes performance-ensuring data which guarantees throughput and/or a permitted time delay. The first node generates packets, each including the data to be transmitted and classification information that indicates the class of that data to be determined according to its required performance, and controls transmission of the packets. The router includes a buffer section configured to store the received packets separately after having classified the packets according to their required performance by reference to the classification information, and a relay controller configured to control transmission of the packets stored in the buffer section at a transmission rate which is equal to or higher than the sum of transmission rates to be guaranteed for every first node associated with the classification information by reference to each piece of the classification information.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Applicant: Panasonic Corporation
    Inventors: Satoru TOKUTSU, Tomoki ISHII, Atsushi YOSHIDA, Takao YAMAGUCHI, Takashi YAMADA
  • Publication number: 20140133307
    Abstract: In a bus system including a bus master, a first bus, and a second bus to connect them together, this router is arranged on the second bus to relay packets. The bus master outputs packets including information about at least one of (N+1) predetermined types of quality requirements. The second bus transmits packets designating at most N types of quality requirements. An exemplary router controls sending of the packets, with respect to at most N types of buffers that classify and store the packets by reference to the quality requirement type information and the packets stored in the buffers, so that the packets are sent in the descending order of their level of the quality requirement. The router controls sending schedule of the traffic flows by sensing a difference between the (N+1) different types of quality requirements.
    Type: Application
    Filed: January 16, 2014
    Publication date: May 15, 2014
    Applicant: Panasonic Corporation
    Inventors: Atsushi YOSHIDA, Satoru TOKUTSU, Tomoki ISHII, Takao YAMAGUCHI
  • Publication number: 20140129750
    Abstract: In a bus control system for a semiconductor circuit, data is transmitted between first and second nodes over a network of buses. The bus controller is connected directly to the first node and includes: a route load detector which detects loads on routes that form at least one of a group of forward routes leading from the first to the second node and a group of backward routes leading from the second to the first node; a candidate route extraction circuit which extracts a candidate route from the group of routes so that loads on the routes that form the group become uniform; a route determining circuit which determines the route to transmit the data based on the candidate route and a predetermined selection rule; and a data communication circuit which transmits the data between the first and second nodes based on header information including route information indicating the route.
    Type: Application
    Filed: January 15, 2014
    Publication date: May 8, 2014
    Applicant: Panasonic Corporation
    Inventors: Tomoki ISHII, Takao YAMAGUCHI, Atsushi YOSHIDA, Satoru TOKUTSU, Yuuki SOGA
  • Patent number: 8670327
    Abstract: A relay device includes a switch for switching a combination of an input for receiving traffic data and an output for sending the traffic data; a congestion information processing section for obtaining congestion information indicating a degree of congestion of each of a plurality of traffics from an adjacent relay device, and congestion information of each traffic in the relay device; a congestion information comparison section for finding information on a congestion level which quantitatively indicates difficulty of flowing of each traffic on a transmission route based on the congestion information obtained from the adjacent relay device and the congestion information of the relay device; a transmission scheduling adjustment section for assigning a transmission band of a bus to each traffic based on the congestion level; and a switch assignment section for shifting the switch based on a result of the assignment of the transmission band of the bus.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: March 11, 2014
    Assignee: Panasonic Corporation
    Inventors: Atsushi Yoshida, Takao Yamaguchi, Tomoki Ishii
  • Publication number: 20140019663
    Abstract: A controller as an embodiment of the present disclosure controls a timing of transmitting an access request that has been received from an initiator (or its transmission interval). The controller includes: transmitting and receiving circuitry configured to receive an access request related to burst accesses from a first initiator that is connected via a first bus to, and adjacent to, the transmitting and receiving circuitry and configured to transmit the access request to a second bus implemented as a network; and a transmission interval controller configured to control the timing of transmitting the access request that has been received from the first initiator according to density of the burst accesses during a period in which the burst accesses continue and an access load on the second bus.
    Type: Application
    Filed: September 16, 2013
    Publication date: January 16, 2014
    Applicant: Panasonic Corporation
    Inventors: Tomoki ISHII, Takao YAMAGUCHI, Atsushi YOSHIDA
  • Publication number: 20130311819
    Abstract: This controller is used in a system in which initiators and targets are connected via distributed buses to control transmission timing of an access request received from the initiators. The controller stores intermittent information including information about an intermittent period in which interference between packets can be restricted and bus operating frequency information indicating a bus operating frequency at which real-time performance is guaranteed for each initiator and which has been generated based on system configuration information and flow configuration information indicating, on a flow basis, a specification required for each initiator to access the target. The controller includes a clock generator; communications circuitry; and transmission interval setting circuitry which sets a time to send transmission permission responsive to a transmission request based on the intermittent period, a time when the transmission request is detected, and a previous transmission time.
    Type: Application
    Filed: July 26, 2013
    Publication date: November 21, 2013
    Applicant: Panasonic Corporation
    Inventors: Tomoki ISHII, Takao YAMAGUCHI, Atsushi YOSHIDA
  • Publication number: 20130294458
    Abstract: An exemplary router is provided for an integrated circuit that has distributed buses and is arranged on a transmission route that leads from a transmission node to a reception node on the distributed buses to relay data. The distributed buses include first and second routes, each leading from the router to the reception node. The router includes a notifying section which sends a data transfer permission request to a second router on the first route and a third router on the second route and which determines whether or not the request is approved before a predetermined standby period passes to see if there is any abnormality in the first and second routes.
    Type: Application
    Filed: July 9, 2013
    Publication date: November 7, 2013
    Inventors: Takao YAMAGUCHI, Atsushi YOSHIDA, Tomoki ISHII
  • Publication number: 20130250792
    Abstract: The router is used to relay a packet to be transmitted from one node to another in an integrated circuit that has distributed buses according to a packet exchange method. The router includes: a plurality of buffers, each of which configured to store packets with information indicating their transmission node; a classifying section configured to classify the buffers that store the packets into a number of groups according to the transmission nodes of the packets; a selecting section configured to select at least one of the buffers of each group; and an output port configured to sequentially output the packets that are stored in the selected buffer.
    Type: Application
    Filed: May 14, 2013
    Publication date: September 26, 2013
    Applicant: Panasonic Corporation
    Inventors: Atsushi YOSHIDA, Tomoki ISHII, Takao YAMAGUCHI
  • Patent number: 8392607
    Abstract: A relay node (203) is a relay node in relay nodes mutually connected through links to compose a communication network, the communication network including paths for transmitting communication data through the relay node (203), including a link status receiving unit (104) which receives at least one link status notification message which is accumulated according to a degree of maintainability of a path, at a time of link disconnecting, at each of the relay devices downstream of the relay device and is forwarded from the downstream relay node (203), a probability generating unit (106) which generates a probability value according to a predetermined probability distribution, a path selection unit (107) which selects one of the paths based on the number of the link status notification message and the probability value, and a relay processing unit (108) which relays the communication data from upstream to a downstream relay device on the path selected by the path selection unit (107).
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: March 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Tomoki Ishii, Takao Yamaguchi, Atsushi Yoshida