Patents by Inventor Tomoko Higashino
Tomoko Higashino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180277456Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.Type: ApplicationFiled: May 21, 2018Publication date: September 27, 2018Inventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
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Patent number: 10002808Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.Type: GrantFiled: December 14, 2016Date of Patent: June 19, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
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Publication number: 20170092554Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.Type: ApplicationFiled: December 14, 2016Publication date: March 30, 2017Inventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
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Publication number: 20150235973Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.Type: ApplicationFiled: April 29, 2015Publication date: August 20, 2015Inventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
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Patent number: 9070560Abstract: A semiconductor wafer with modified regions formed in the substrate is provided. A modified region is formed apart from the side of a wafer and a pad is formed over an insulating film, which is formed over the main surface of the substrate of the wafer. Further, the modified region is formed closer to the side surface of the substrate than the pad. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.Type: GrantFiled: May 23, 2014Date of Patent: June 30, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
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Patent number: 9006036Abstract: To provide a semiconductor device having an improved quality. The semiconductor device of the invention has a tape substrate having a semiconductor chip thereon, a plurality of land pads placed around the semiconductor chip, a plurality of wires for electrically coupling the electrode pad of the semiconductor chip to the land pad, and a plurality of terminal portions provided on the lower surface of the tape substrate. An average distance between local peaks of the surface roughness of a first region between the land pad of the tape substrate and the semiconductor chip is smaller than an average distance of local peaks of the surface roughness of a second region between the land pad of the tape substrate and the first region.Type: GrantFiled: September 18, 2013Date of Patent: April 14, 2015Assignee: Renesas Electronics CorporationInventors: Tomoko Higashino, Yuichi Morinaga, Kazuya Tsuboi, Tamaki Wada
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Publication number: 20140252643Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
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Patent number: 8772135Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.Type: GrantFiled: December 2, 2011Date of Patent: July 8, 2014Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
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Publication number: 20140080260Abstract: To provide a semiconductor device having an improved quality. The semiconductor device of the invention has a tape substrate having a semiconductor chip thereon, a plurality of land pads placed around the semiconductor chip, a plurality of wires for electrically coupling the electrode pad of the semiconductor chip to the land pad, and a plurality of terminal portions provided on the lower surface of the tape substrate. An average distance between local peaks of the surface roughness of a first region between the land pad of the tape substrate and the semiconductor chip is smaller than an average distance of local peaks of the surface roughness of a second region between the land pad of the tape substrate and the first region.Type: ApplicationFiled: September 18, 2013Publication date: March 20, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tomoko HIGASHINO, Yuichi MORINAGA, Kazuya TSUBOI, Tamaki WADA
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Publication number: 20120077332Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.Type: ApplicationFiled: December 2, 2011Publication date: March 29, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
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Patent number: 8084334Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.Type: GrantFiled: January 31, 2011Date of Patent: December 27, 2011Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
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Publication number: 20110124180Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.Type: ApplicationFiled: January 31, 2011Publication date: May 26, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
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Patent number: 7892949Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.Type: GrantFiled: November 9, 2006Date of Patent: February 22, 2011Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
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Publication number: 20100213594Abstract: A semiconductor device having a structure in which the structure is laminated in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of the other semiconductor chip by the adhesive layer of the back surface, a semiconductor device having a structure in which the semiconductor device is laminated in many stages is manufactured.Type: ApplicationFiled: May 4, 2010Publication date: August 26, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Tomoko Higashino, Chuichi Miyazaki, Yoshiyuki Abe
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Publication number: 20090191667Abstract: A semiconductor device having a structure in which the structure is laminated in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of the other semiconductor chip by the adhesive layer of the back surface, a semiconductor device having a structure in which the semiconductor device is laminated in many stages is manufactured.Type: ApplicationFiled: March 23, 2009Publication date: July 30, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Tomoko HIGASHINO, Chuichi MIYAZAKI, Yoshiyuki ABE
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Patent number: 7563642Abstract: A semiconductor wafer is mounted onto a dicing tape, the dicing tape comprising a first tape easy to stretch and a second tape difficult to stretch and provided on the first tape. Thereafter, a ring-shaped jig is mounted onto the dicing tape along the outer periphery of the semiconductor wafer and the semiconductor wafer is diced. Subsequently, the dicing tape is stretched from the outer periphery thereof to widen the spacing between adjacent chips. Thus, the dicing tape is stretched from its outer periphery in a state in which there are formed an area of the dicing tape underlying the semiconductor wafer and easy to stretch and an area of the dicing tape located along the outer periphery of the wafer and difficult to stretch. Consequently, the force of stretching the dicing tape is transmitted to the semiconductor wafer-mounted area of the first tape, thus permitting pickup of each chip in a sufficiently widened state of the spacing between adjacent chip-forming areas.Type: GrantFiled: January 24, 2007Date of Patent: July 21, 2009Assignee: Renesas Technology Corp.Inventor: Tomoko Higashino
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Publication number: 20090121337Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.Type: ApplicationFiled: November 9, 2006Publication date: May 14, 2009Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
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Patent number: 7514294Abstract: The semiconductor device having the structure which laminated the chip in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of an other semiconductor chip by the adhesive layer of the back surface, the semiconductor device having the structure for which the semiconductor chip was laminated by many stages is manufactured.Type: GrantFiled: August 9, 2006Date of Patent: April 7, 2009Assignee: Renesas Technology Corp.Inventors: Tomoko Higashino, Chuichi Miyazaki, Yoshiyuki Abe
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Publication number: 20070218651Abstract: A semiconductor wafer is mounted onto a dicing tape, the dicing tape comprising a first tape easy to stretch and a second tape difficult to stretch and provided on the first tape. Thereafter, a ring-shaped jig is mounted onto the dicing tape along the outer periphery of the semiconductor wafer and the semiconductor wafer is diced. Subsequently, the dicing tape is stretched from the outer periphery thereof to widen the spacing between adjacent chips. Thus, the dicing tape is stretched from its outer periphery in a state in which there are formed an area of the dicing tape underlying the semiconductor wafer and easy to stretch and an area of the dicing tape located along the outer periphery of the wafer and difficult to stretch. Consequently, the force of stretching the dicing tape is transmitted to the semiconductor wafer-mounted area of the first tape, thus permitting pickup of each chip in a sufficiently widened state of the spacing between adjacent chip-forming areas.Type: ApplicationFiled: January 24, 2007Publication date: September 20, 2007Inventor: Tomoko Higashino
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Publication number: 20070114672Abstract: The miniaturization of the system in package which laminates a plurality of semiconductor chips on a wiring substrate via a die attach film is promoted. In the system in package (SiP) which laminates memory chips and microcomputer chip via die attach film on wiring substrate, by forming metal plate in the chip mounting region of wiring substrate, and mounting memory chip of an undermost layer on this metal plate, the flatness of the chip mounting region of wiring substrate is secured, and die attach film which intervenes between metal plate and memory chip of an undermost layer is made the same quality as die attach film which intervenes between chips (between memory chips and between memory chip and microcomputer chips), and the same thickness.Type: ApplicationFiled: October 20, 2006Publication date: May 24, 2007Inventors: Tomoko Higashino, Hirotaka Nishizawa, Tamaki Wada, Chuichi Miyazaki