Patents by Inventor Tomoko Higashino

Tomoko Higashino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180277456
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 27, 2018
    Inventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
  • Patent number: 10002808
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 19, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • Publication number: 20170092554
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: December 14, 2016
    Publication date: March 30, 2017
    Inventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
  • Publication number: 20150235973
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: April 29, 2015
    Publication date: August 20, 2015
    Inventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
  • Patent number: 9070560
    Abstract: A semiconductor wafer with modified regions formed in the substrate is provided. A modified region is formed apart from the side of a wafer and a pad is formed over an insulating film, which is formed over the main surface of the substrate of the wafer. Further, the modified region is formed closer to the side surface of the substrate than the pad. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: June 30, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • Patent number: 9006036
    Abstract: To provide a semiconductor device having an improved quality. The semiconductor device of the invention has a tape substrate having a semiconductor chip thereon, a plurality of land pads placed around the semiconductor chip, a plurality of wires for electrically coupling the electrode pad of the semiconductor chip to the land pad, and a plurality of terminal portions provided on the lower surface of the tape substrate. An average distance between local peaks of the surface roughness of a first region between the land pad of the tape substrate and the semiconductor chip is smaller than an average distance of local peaks of the surface roughness of a second region between the land pad of the tape substrate and the first region.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: April 14, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoko Higashino, Yuichi Morinaga, Kazuya Tsuboi, Tamaki Wada
  • Publication number: 20140252643
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: May 23, 2014
    Publication date: September 11, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
  • Patent number: 8772135
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: July 8, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • Publication number: 20140080260
    Abstract: To provide a semiconductor device having an improved quality. The semiconductor device of the invention has a tape substrate having a semiconductor chip thereon, a plurality of land pads placed around the semiconductor chip, a plurality of wires for electrically coupling the electrode pad of the semiconductor chip to the land pad, and a plurality of terminal portions provided on the lower surface of the tape substrate. An average distance between local peaks of the surface roughness of a first region between the land pad of the tape substrate and the semiconductor chip is smaller than an average distance of local peaks of the surface roughness of a second region between the land pad of the tape substrate and the first region.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 20, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoko HIGASHINO, Yuichi MORINAGA, Kazuya TSUBOI, Tamaki WADA
  • Publication number: 20120077332
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: December 2, 2011
    Publication date: March 29, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki ABE, Chuichi MIYAZAKI, Hideo MUTOU, Tomoko HIGASHINO
  • Patent number: 8084334
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: December 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • Publication number: 20110124180
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: January 31, 2011
    Publication date: May 26, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • Patent number: 7892949
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: February 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • Publication number: 20100213594
    Abstract: A semiconductor device having a structure in which the structure is laminated in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of the other semiconductor chip by the adhesive layer of the back surface, a semiconductor device having a structure in which the semiconductor device is laminated in many stages is manufactured.
    Type: Application
    Filed: May 4, 2010
    Publication date: August 26, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Tomoko Higashino, Chuichi Miyazaki, Yoshiyuki Abe
  • Publication number: 20090191667
    Abstract: A semiconductor device having a structure in which the structure is laminated in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of the other semiconductor chip by the adhesive layer of the back surface, a semiconductor device having a structure in which the semiconductor device is laminated in many stages is manufactured.
    Type: Application
    Filed: March 23, 2009
    Publication date: July 30, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Tomoko HIGASHINO, Chuichi MIYAZAKI, Yoshiyuki ABE
  • Patent number: 7563642
    Abstract: A semiconductor wafer is mounted onto a dicing tape, the dicing tape comprising a first tape easy to stretch and a second tape difficult to stretch and provided on the first tape. Thereafter, a ring-shaped jig is mounted onto the dicing tape along the outer periphery of the semiconductor wafer and the semiconductor wafer is diced. Subsequently, the dicing tape is stretched from the outer periphery thereof to widen the spacing between adjacent chips. Thus, the dicing tape is stretched from its outer periphery in a state in which there are formed an area of the dicing tape underlying the semiconductor wafer and easy to stretch and an area of the dicing tape located along the outer periphery of the wafer and difficult to stretch. Consequently, the force of stretching the dicing tape is transmitted to the semiconductor wafer-mounted area of the first tape, thus permitting pickup of each chip in a sufficiently widened state of the spacing between adjacent chip-forming areas.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: July 21, 2009
    Assignee: Renesas Technology Corp.
    Inventor: Tomoko Higashino
  • Publication number: 20090121337
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 14, 2009
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • Patent number: 7514294
    Abstract: The semiconductor device having the structure which laminated the chip in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of an other semiconductor chip by the adhesive layer of the back surface, the semiconductor device having the structure for which the semiconductor chip was laminated by many stages is manufactured.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: April 7, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Tomoko Higashino, Chuichi Miyazaki, Yoshiyuki Abe
  • Publication number: 20070218651
    Abstract: A semiconductor wafer is mounted onto a dicing tape, the dicing tape comprising a first tape easy to stretch and a second tape difficult to stretch and provided on the first tape. Thereafter, a ring-shaped jig is mounted onto the dicing tape along the outer periphery of the semiconductor wafer and the semiconductor wafer is diced. Subsequently, the dicing tape is stretched from the outer periphery thereof to widen the spacing between adjacent chips. Thus, the dicing tape is stretched from its outer periphery in a state in which there are formed an area of the dicing tape underlying the semiconductor wafer and easy to stretch and an area of the dicing tape located along the outer periphery of the wafer and difficult to stretch. Consequently, the force of stretching the dicing tape is transmitted to the semiconductor wafer-mounted area of the first tape, thus permitting pickup of each chip in a sufficiently widened state of the spacing between adjacent chip-forming areas.
    Type: Application
    Filed: January 24, 2007
    Publication date: September 20, 2007
    Inventor: Tomoko Higashino
  • Publication number: 20070114672
    Abstract: The miniaturization of the system in package which laminates a plurality of semiconductor chips on a wiring substrate via a die attach film is promoted. In the system in package (SiP) which laminates memory chips and microcomputer chip via die attach film on wiring substrate, by forming metal plate in the chip mounting region of wiring substrate, and mounting memory chip of an undermost layer on this metal plate, the flatness of the chip mounting region of wiring substrate is secured, and die attach film which intervenes between metal plate and memory chip of an undermost layer is made the same quality as die attach film which intervenes between chips (between memory chips and between memory chip and microcomputer chips), and the same thickness.
    Type: Application
    Filed: October 20, 2006
    Publication date: May 24, 2007
    Inventors: Tomoko Higashino, Hirotaka Nishizawa, Tamaki Wada, Chuichi Miyazaki