Abstract: Provided is an Fe—Pt—BN-based sputtering target that has a high relative density and that suppresses particle generation. The Fe—Pt—BN-based sputtering target has, as a residue after dissolution in aqua regia measured by a procedure below, the particle size distribution in which D90 is 5.5 ?m or less and a proportion of fine particles smaller than 1 ?m is 35% or less. The procedure includes: (1) cutting out an about 4 mm-square sample piece from the sputtering target, followed by pulverizing to prepare a pulverized product; (2) classifying the pulverized product using sieves of 106 ?m and 300 ?m in opening size and collecting a powder that has passed through the 300 ?m sieve and remained on the 106 ?m sieve; (3) immersing the powder in aqua regia heated to 200° C. to prepare a residue-containing solution in which the powder has been dissolved; (4) filtering the residue-containing solution through a 5A filter paper specified in JIS P 3801 and drying a residue on the filter paper at 80° C.

Abstract: A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below.

Abstract: An object of the present invention is to provide an activated blood coagulation factor X (FXa) inhibitor that reduces the risk of bleeding caused by the treatment of thromboembolism. The present invention provides an oral anticoagulant agent comprising a compound represented by the following formula (1): or a pharmacologically acceptable salt thereof, or a hydrate thereof, as an active ingredient, wherein (A) a factor involved in the risk of bleeding caused by the anticoagulant agent is selected as a dose determinant; (B) a reference value of the dose determinant is set; (C) the dose determinant of a patient in need of administration is measured; and (D) the dose of the anticoagulant agent is selected with the reference value as an index.

Abstract: A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below.

Abstract: A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below.

Abstract: A nonvolatile semiconductor memory device (and method of forming same) includes a word gate provided above a channel region of a semiconductor substrate via an insulating layer, a control gate provided at a side of the word gate, and a charge storage layer provided by an ONO film between the channel region and the control gate, and between the word gate and the control gate. The control gate includes a silicide layer including silicide containing nickel, and a non-silicide layer provided between the silicide layer and the charge storage layer.

Abstract: A method for manufacturing transistors includes forming a gate electrode and a side wall insulating film over the device-forming surface of a silicon substrate. A source/drain region is formed in a periphery of the gate electrode on the silicon substrate. A Ni film is formed on the entire device-forming surface of the silicon substrate that is provided with a side wall formed thereon, and then, a reaction of the silicon substrate with the Ni film on the source/drain region by heating the silicon substrate. Unreacted portions of the Ni film are removed, and a Ni silicide layer is formed on the source/drain region. During forming the Ni film or during inducing a reaction of the silicon substrate with the Ni film by heating the silicon substrate, a broken portion, which is provided by breaking the Ni film off, is formed on the side wall.

Abstract: Method for manufacturing a semiconductor device, includes: forming a layer of dicobalt monosilicide (Co2Si) or of cobalt (Co) on a device-forming surface of a silicon substrate in a sputter apparatus, by utilizing a predetermined temperature profile; elevating a temperature of the silicon substrate to a predetermined temperature T2, which is equal to or higher than 600° C., conducted after forming the layer of Co or Co2Si; and forming a layer of monocobalt monosilicide (CoSi) on the device-forming surface of the silicon substrate at a temperature equal to or higher than T2, conducted after heating the silicon substrate to T2, wherein, the silicon substrate is elevated to a temperature between a highest reachable temperature T1 of the silicon substrate during forming the layer of Co or Co2Si and the temperature T2 at a temperature ramp rate of equal to or higher than 50° C./sec.

Abstract: A junction leak current of a transistor including a silicide layer provided on a source/drain region is to be suppressed. After forming a gate electrode over a chip-side surface of a silicon substrate, an insulating layer is formed over the gate electrode. The insulating layer is etched back so as to form a sidewall that covers the sidewall of the gate electrode, and a region adjacent to the sidewall on the chip-side surface of the silicon substrate, where a source/drain region is to be formed, is etched so as to form a generally horizontal scraped section on the chip-side surface. Then a dopant is implanted to the silicon substrate around the gate electrode, to thereby form the source/drain region. On the chip-side surface of the silicon substrate where the gate electrode is provided, a Ni layer is formed, so that the Ni layer is reacted with the silicon substrate thus to form a Ni-silicide layer.

Abstract: A method for improved manufacturing stability of transistors having silicide layers is provided. A gate electrode 105 and a side wall insulating film that covers a side surface of the gate electrode are formed over the device-forming surface of a silicon substrate 101. A source/drain region 109 is formed in a periphery of the gate electrode 105 on the silicon substrate 101. A Ni film 115 is formed on the entire device-forming surface of the silicon substrate 101 that is provided with a side wall 107 formed thereon, and then, a reaction of the silicon substrate 101 with the Ni film 115 on the source/drain region 109 by heating the silicon substrate 101. Thereafter, unreacted portions of the Ni film 115 are removed, and then a Ni silicide layer 111 is formed on the source/drain region 109.

Abstract: A method of manufacturing a semiconductor device that can inhibit transformation of an NiSi layer into a disilicide is to be provided. An NiSi layer is formed on gate electrodes and source/drain regions in both of a P-MOS transistor and a N-MOS transistor (a silicide layer formation step). A direct nitride layer is formed on an entire region including the NiSi layer (a nitride layer formation step). Then an element that can increase heat-resisting temperature of the NiSi layer is implanted into the NiSi layer (an element implantation step). As a result, heat-resisting property of the NiSi layer can be increased, and thereby the NiSi layer can be inhibited from being transformed into a disilicide.

Abstract: A semiconductor device includes a silicon substrate, and a NiSi layer provided on the silicon substrate aiming to suppress oxidation of the surface of a NiSi layer and the resistivity increase. The NiSi layer includes a bottom NiSi region and a top NiSi region. The bottom NiSi region provided in contact with silicon surface, and containing substantially no nitrogen. The top NiSi region is a nitrided NiSi region provided in contact with the bottom NiSi region, and containing nitrogen. The NiSi layer has a total thickness of 50 nm or below.

Abstract: A junction leak current of a transistor including a silicide layer provided on a source/drain region is to be suppressed. After forming a gate electrode over a chip-side surface of a silicon substrate, an insulating layer is formed over the gate electrode. The insulating layer is etched back so as to form a sidewall that covers the sidewall of the gate electrode, and a region adjacent to the sidewall on the chip-side surface of the silicon substrate, where a source/drain region is to be formed, is etched so as to form a generally horizontal scraped section on the chip-side surface. Then a dopant is implanted to the silicon substrate around the gate electrode, to thereby form the source/drain region. On the chip-side surface of the silicon substrate where the gate electrode is provided, a Ni layer is formed, so that the Ni layer is reacted with the silicon substrate thus to form a Ni-silicide layer.

Abstract: Method for manufacturing a semiconductor device, includes: forming a layer of dicobalt monosilicide (Co2Si) or of cobalt (Co) on a device-forming surface of a silicon substrate in a sputter apparatus, by utilizing a predetermined temperature profile; elevating a temperature of the silicon substrate to a predetermined temperature T2, which is equal to or higher than 600° C., conducted after forming the layer of Co or Co2Si; and forming a layer of monocobalt monosilicide (CoSi) on the device-forming surface of the silicon substrate at a temperature equal to or higher than T2, conducted after heating the silicon substrate to T2, wherein, the silicon substrate is elevated to a temperature between a highest reachable temperature T1 of the silicon substrate during forming the layer of Co or Co2Si and the temperature T2 at a temperature ramp rate of equal to or higher than 50° C./sec.

Abstract: In the method for manufacturing the semiconductor device including a salicide film, prior to the process for forming the salicide film (S30), the operation for protecting the oxide film is conducted in order to prevent the scattering of the oxide film on silicon substrate (S10). Then, the operation for cleaning the surface of the silicon substrate is conducted via a dry etch (S20). Thereafter, the salicide film is formed (S30). Thereby reliability of the semiconductor device including the salicide film is enhanced.

Abstract: A method of manufacturing a semiconductor device that can inhibit transformation of an NiSi layer into a disilicide is to be provided. An NiSi layer is formed on gate electrodes and source/drain regions in both of a P-MOS transistor and a N-MOS transistor (a silicide layer formation step). A direct nitride layer is formed on an entire region including the NiSi layer (a nitride layer formation step). Then an element that can increase heat-resisting temperature of the NiSi layer is implanted into the NiSi layer (an element implantation step). As a result, heat-resisting property of the NiSi layer can be increased, and thereby the NiSi layer can be inhibited from being transformed into a disilicide.

Abstract: An ion implantation method is disclosed which can suppress point defects in a crystal semiconductor material that can arise from ion implantation in a semiconductor device manufacturing process. According to an embodiment, in a semiconductor device manufacturing process, in the place of an ion implantation step of a heavy ion, such as indium (In), in which the channeling phenomenon does not substantially occur in the formation of a pocket diffusion layer region, such a heavy ion can be implanted so that an implant angle (3) becomes 50°±6° with respect to an exposed Si (100) face of an Si (100) substrate (2). Then, implanted ions can be activation with a thermal treatment step to form a pocket diffusion layer region.

Abstract: A method for forming a MOSFET includes the step of forming deep SD regions and ordinary SD regions by ion-implantation using a gate structure having a gate electrode and associated side walls as a mask, removing the side walls from the gate electrode, forming SD extension regions and pocket regions by ion-implantation using the gate electrode as a mask, and forming other side walls on the gate electrode.

Abstract: When the temperature of a silicon substrate is increased, a first annealing gas which is mainly composed of argon or the like that does not react with said silicon substrate with a trace of oxygen added thereto, is supplied to the position of the silicon substrate to prevent any unwanted reaction from occurring on the silicon substrate whose temperature is increasing. When the temperature of the silicon substrate is lowered, a second annealing gas which is mainly composed of nitrogen or the like which has a high thermal conductivity is supplied to the silicon substrate to quickly lower the temperature of the silicon substrate and prevent a doped impurity from being undesirably diffused.

Abstract: A silicon substrate including an impurity doped thereinto is raised in temperature to a predetermined annealing temperature, and then the temperature of the silicon substrate reaching the annealing temperature is decreased at variable speeds such that the temperature is decreased at a high speed initially and a low speed latterly. The temperature of the silicon substrate is decreased at such a speed as the impurity with a reduced solid solubility due to the decreased temperature is not acted upon by thermal energy to disconnect the impurity from the silicon substrate.