Patents by Inventor Tomoko Matsuda

Tomoko Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020006693
    Abstract: A manufacturing method that prevents an enhanced diffusion while preventing channeling from occurring, and forms a local channel having a steep impurity concentration distribution with precise positioning. After forming a sacrifice film on the surface of a silicon substrate, ion implantation is performed from a perpendicular direction through a resist film mask to form a local channel. The thickness of the sacrifice film is greater than or equal to 10 nm and less than or equal to 100 nm. Indium is used as an ion species of the ion implantation.
    Type: Application
    Filed: July 12, 2001
    Publication date: January 17, 2002
    Applicant: NEC CORPORATION
    Inventor: Tomoko Matsuda
  • Patent number: 6319734
    Abstract: A method for establishing conditions of making an index representing characteristics of a MOSFET in a permitted range by means of differentially injecting ions into a wafer. The method includes the steps of: making a curve indicating an amount of energy contamination with respect to a junction depth, and determining a permitted amount of energy contamination with respect to a desired junction depth. A MOSFET having substantially no deterioration of the characteristics can be obtained by referring to the curve, and establishing a degree of vacuum of and/or a distance of a beam line.
    Type: Grant
    Filed: December 1, 1999
    Date of Patent: November 20, 2001
    Assignee: NEC Corporation
    Inventor: Tomoko Matsuda
  • Publication number: 20010034095
    Abstract: The present invention provides a method of forming a diffusion region in a semiconductor region. The method comprises the steps of: carrying out a first ion-implantation of a first impurity of a first conductivity type into the semiconductor region to form an ion-implanted region which is in non-amorphous state, wherein first type clusters of the first impurity are formed in the ion-implanted region; carrying out a second ion-implantation of a second impurity of the first conductivity type into the ion-implanted region, wherein second type clusters of the first and second impurities are formed in the ion-implanted region; and carrying out a heat treatment for activating the first and second impurities in the ion-implanted region to change the ion-implanted region into a diffusion region.
    Type: Application
    Filed: January 10, 2001
    Publication date: October 25, 2001
    Applicant: NEC Corporation
    Inventor: Tomoko Matsuda
  • Publication number: 20010031544
    Abstract: When the temperature of a silicon substrate is increased, a first annealing gas which is mainly composed of argon or the like that does not react with said silicon substrate with a trace of oxygen added thereto, is supplied to the position of the silicon substrate to prevent any unwanted reaction from occurring on the silicon substrate whose temperature is increasing. When the temperature of the silicon substrate is lowered, a second annealing gas which is mainly composed of nitrogen or the like which has a high thermal conductivity is supplied to the silicon substrate to quickly lower the temperature of the silicon substrate and prevent a doped impurity from being undesirably diffused.
    Type: Application
    Filed: April 10, 2001
    Publication date: October 18, 2001
    Inventor: Tomoko Matsuda
  • Publication number: 20010031537
    Abstract: A silicon substrate including an impurity doped thereinto is raised in temperature to a predetermined annealing temperature, and then the temperature of the silicon substrate reaching the annealing temperature is decreased at variable speeds such that the temperature is decreased at a high speed initially and a low speed latterly. The temperature of the silicon substrate is decreased at such a speed as the impurity with a reduced solid solubility due to the decreased temperature is not acted upon by thermal energy to disconnect the impurity from the silicon substrate.
    Type: Application
    Filed: April 12, 2001
    Publication date: October 18, 2001
    Applicant: NEC Corporation
    Inventor: Tomoko Matsuda