Abstract: Control logic in a memory device cause a programming pulse to be applied to a set of wordlines including a first set of even-numbered wordlines corresponding to a first set of memory cells to be erased and a second set of odd-numbered wordlines corresponding to a second set of memory cells to be erased, where a set of electrons are injected into a first set of gate regions, a second set of gate regions, and a set of inter-cell regions of a charge trap (CT) layer of the memory device. The control logic executes a first erase cycle on the first set of even-numbered wordlines to remove a first subset of electrons from the first set of gate regions corresponding to the first set of even-numbered wordlines. The control logic executes a second erase cycle on the second set of odd-numbered wordlines to remove a second subset of electrons from the second set of gate regions corresponding to the second set of even-numbered wordlines.

Abstract: Described are systems and methods for concurrent slow-fast memory cell programming.

Abstract: A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit lines are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.

Abstract: A memory system includes a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys and a value data block. The memory system further includes a processing device that receives an input search key and identifies one of the plurality of stored search keys that matches the input search key, the one of the plurality of stored search keys having an associated match location in the CAM block. The processing device further determines, using the associated match location, a corresponding value location in the value data block and retrieves, from the value location in the value data block, data representing a value associated with the input search key.

Abstract: A memory device includes a memory array configured as quad-level cell (QLC) memory and a control logic operatively coupled to the memory array. The control logic identifies a first two bits of particular pages of a QLC logical state. The control logic causes memory cells of the memory array to be coarse programmed with a threshold voltage distribution of a multi-level cell (MLC) logical state corresponding to the first two bits. The control logic reads the MLC logical state from the memory cells and a second two bits from a cache buffer to determine the QLC logical state. The control logic causes the memory cells to be further coarse programmed with a QLC threshold voltage distribution corresponding to the QLC logical state.

Abstract: Control logic in a memory device identifies a set of memory cells in a block of a memory array, wherein the set of memory cells comprises two or more memory cells programmed during a program phase of a program operation and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a program verify phase of the program operation and performs concurrent sensing operations on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.

Abstract: Methods and devices related to a cellular signal mesh network are described. In an example, a method can include determining, via a processing resource of a first computing device, whether a cellular signal of the first computing device is below a threshold cellular signal, transmitting from the first computing device to a second computing device first signaling including data representing a request for operational data of the second computing device in response to determining that the cellular signal of the first computing device is below the threshold cellular signal, receiving from the second computing device second signaling comprising the operational data of the second computing device, and transmitting from the first computing device to the second computing device third signaling including data representing at least one of: a voice call, a video call, or a message in response to receiving the second signaling comprising the operational data.

Abstract: A memory device includes a content addressable memory (CAM) block storing a plurality of stored search keys. The memory device further includes control logic that determines a first number of memory cells in at least one string of the CAM block storing one of the plurality of stored search keys, the first number of memory cells storing a first logical value, and stores a calculated parity value representing the first number of memory cells in a page cache associated with the CAM block. The control logic further reads stored parity data from one or more memory cells in the at least one string, the one or more memory cells connected to one or more additional wordlines in the CAM block, and compares the calculated parity value to the stored parity data to determine whether an error is present in the one of the plurality of stored search keys in the CAM block.

Abstract: A memory system includes a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys. The memory system further includes a processing device that receives an input search key and identifies, from the plurality of stored search keys in the CAM block, multiple redundant copies of a stored search key that match the input search key. The processing device further determining whether a number of the multiple redundant copies of the stored search key that match the input search key satisfies a threshold criterion. Responsive to the number of the multiple redundant copies of the stored search key that match the input search key satisfying the threshold criterion, the processing device determines a match result for the input search key.

Abstract: A memory system includes a memory device comprising a programming buffer and a content addressable memory (CAM) block. The memory system further includes a processing device that receives a plurality of data entries to be stored at the memory device and stores the plurality of data entries in a plurality of pages of the programming buffer, each of the plurality of pages of the programming buffer comprising a respective subset of the plurality of data entries. The processing device further initiates a conversion operation to copy the plurality of data entries from the programming buffer to the CAM block. The conversion operation includes reading respective portions of each data entry in each respective subset of the plurality of data entries from the plurality of pages of the programming buffer, and writing the respective portions to respective CAM pages of the CAM block.

Abstract: Control logic in a memory device initiates a program operation including a first phase including applying a ramping voltage level to a set of wordlines of a memory device to boost a set of pillar voltages and a second phase including applying a set of programming pulses to a wordline associated with one or more memory cells of the memory device to be programmed to a set of programming levels, wherein each programming level of the set of programming levels is programmed by each programming pulse. During the first phase of the program operation, a first voltage applied to a drain-side select line (SGD) is adjusted from a first SGD voltage level to a second SGD voltage level.

Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.

Abstract: A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit lines are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

Abstract: A request to execute a programming operation to program multiple sub-blocks including a first sub-block and a second sub-block of a memory device is identified. A first drive operation is executed to load first data into a first select gate drain (SGD) associated with the first sub-block. Following completion of the first drive operation, a second drive operation is executed to load second data into a second SGD associated with the second sub-block. Following completion of the second drive operation, a third drive operation is executed to re-load the first data into the first SGD.

Abstract: A request to execute a programming operation to program multiple sub-blocks including a first sub-block and a second sub-block of a memory device is identified. A first drive operation is executed to load first data into a first select gate drain (SGD) associated with the first sub-block. One or more program bias disturb mitigation operations are executed in association with a second drive operation to load second data into a second SGD associated with the second sub-block.

Abstract: A memory system includes a memory device comprising a programming buffer and a content addressable memory (CAM) block. The memory system further includes a processing device that receives a plurality of data entries to be stored at the memory device and stores the plurality of data entries in a plurality of pages of the programming buffer, each of the plurality of pages of the programming buffer comprising a respective subset of the plurality of data entries. The processing device further initiates a conversion operation to copy the plurality of data entries from the programming buffer to the CAM block. The conversion operation includes reading respective portions of each data entry in each respective subset of the plurality of data entries from the plurality of pages of the programming buffer, and writing the respective portions to respective CAM pages of the CAM block.

Abstract: Control logic in a memory device, identifies a set of a plurality of memory cells associated with a selected wordline to be programmed to respective programming levels during a program operation and causes a set of a plurality of pillars with which the set of the plurality of memory cells are associated to be boosted to respective pillar voltages corresponding to the respective programming levels.

Abstract: Control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. At a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. At a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. In view of the second data, a level shifting operation associated with the memory cell is caused to be executed.

Abstract: Control logic in a memory device identifies a set of memory cells in a block of a memory array, wherein the set of memory cells comprises two or more memory cells programmed during a program phase of a program operation and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a program verify phase of the program operation and performs concurrent sensing operations on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.