Patents by Inventor Tomoko Ogura Iwasaki

Tomoko Ogura Iwasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210280250
    Abstract: A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a representation of the input search word and a representation of an inverse of the input search word. The search pattern is provided as input to search lines of a ternary content-addressable memory (TCAM) block. A subset of the search lines is set to a logical high state based on a first portion of the input search word being designated as don't-care bits. The search pattern causes at least one string in the CAM block to be conductive and provide a signal in response to a data entry stored on the string comprising a second portion of the input search word that excludes the don't-care bits. A location of the data entry is determined and output.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 9, 2021
    Inventors: Manik Advani, Tomoko Ogura Iwasaki
  • Publication number: 20210272630
    Abstract: A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a first set of signals representing the input search word and a second set of signals representing a second sequence of bits comprising an inverse of the first sequence of bits. The search pattern is provided as input to search lines of a content addressable memory (CAM) block. The search pattern causes at least one string in the CAM block to be conductive and provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string. A location of the data entry is determined based on data read from the page buffer and the location is output.
    Type: Application
    Filed: May 12, 2021
    Publication date: September 2, 2021
    Inventors: Tomoko Ogura Iwasaki, Manik Advani
  • Publication number: 20210255960
    Abstract: Various embodiments described herein provide for a page program sequence for a block of a memory device, such as a negative-and (NAND)-type memory device, where all the wordlines are programmed with respect to a given set of page types (e.g., LP pages) prior to wordlines are programmed with respect to a next set of page types (e.g., UP and XP pages).
    Type: Application
    Filed: August 20, 2020
    Publication date: August 19, 2021
    Inventors: Kulachet Tanpairoj, Jianmin Huang, Tomoko Ogura Iwasaki, Kishore Kumar Muchherla, Peter Sean Feeley
  • Patent number: 11087851
    Abstract: Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Zhengyi Zhang, Dan Xu, Tomoko Ogura Iwasaki
  • Publication number: 20210201993
    Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.
    Type: Application
    Filed: September 3, 2020
    Publication date: July 1, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Dan Xu, Jun Xu, Erwin E. Yu, Paolo Tessariol, Tomoko Ogura Iwasaki
  • Publication number: 20210202017
    Abstract: Memories having a first pool of memory cells having a first storage density and a second pool of memory cells having a second storage density greater than the first storage density, and a controller configured to cause the memory to determine whether a value of an indication of available power of a power supply for the memory is less than a threshold, and in response to determining that the value of the indication of available power is less than the threshold, increase a size of the first pool of memory cells, limit programming of data received by the memory to the first pool of memory cells, and cease movement of data from the first pool of memory cells to the second pool of memory cells, as well as apparatus including similar memories.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Avani F. Trivedi, Tracy D. Evans, Carla L. Christensen, Tomoko Ogura Iwasaki, Aparna U. Limaye
  • Publication number: 20210202000
    Abstract: A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a first set of signals representing the input search word and a second set of signals representing a second sequence of bits comprising an inverse of the first sequence of bits. The search pattern is provided as input to search lines of a content addressable memory (CAM) block. The search pattern causes at least one string in the CAM block to be conductive and provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string. A location of the data entry is determined based on data read from the page buffer and the location is output.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 1, 2021
    Inventors: Tomoko Ogura Iwasaki, Manik Advani
  • Publication number: 20210202009
    Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval.
    Type: Application
    Filed: August 12, 2020
    Publication date: July 1, 2021
    Inventors: Kalyan Chakravarthy Kavalipurapu, Tomoko Ogura Iwasaki, Erwin E. Yu, Hong-Yan Chen, Yunfei Xu
  • Publication number: 20210202013
    Abstract: Apparatus having a string of series-connected memory cells comprising a plurality of principal memory cells and a plurality of dummy memory cells might have a controller configured to cause the apparatus to apply a first programming pulse to a particular dummy memory cell of the plurality of dummy memory cells sufficient to increase a threshold voltage of the particular dummy memory cell to a voltage level sufficient to cause the particular dummy memory cell to remain deactivated during a read operation on the string of series-connected memory cells, and to concurrently apply a second programming pulse to each principal memory cell of the plurality of principal memory cell sufficient to increase threshold voltages of at least a portion of the plurality of principal memory cells.
    Type: Application
    Filed: June 8, 2020
    Publication date: July 1, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Zhengyi Zhang, Dan Xu, Tomoko Ogura Iwasaki
  • Publication number: 20210200889
    Abstract: An access request is received. The access request comprises a physical page address corresponding to a primary memory block of a memory device, an input security key, and a logical page address corresponding to the physical page address. The input security key is provided as input to a (CAM) block that stores a plurality of security keys to verify that the input security key matches a stored security key. A location of the stored security key is checked to verify that it corresponds to the logical page address included in the access request based a predetermined mapping. Based on verifying that the stored security key corresponds to the logical page address included in the access request, the physical page address corresponding to the primary memory block is accessed.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 1, 2021
    Inventors: Tomoko Ogura Iwasaki, Manik Advani, Samir Mittal
  • Patent number: 11031080
    Abstract: A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a first set of signals representing the input search word and a second set of signals representing a second sequence of bits comprising an inverse of the first sequence of bits. The search pattern is provided as input to search lines of a content addressable memory (CAM) block. The search pattern causes at least one string in the CAM block to be conductive and provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string. A location of the data entry is determined based on data read from the page buffer and the location is output.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tomoko Ogura Iwasaki, Manik Advani
  • Patent number: 10950313
    Abstract: Methods of operating a memory having a first pool of memory cells having a first storage density and a second pool of memory cells having a second storage density greater than the first storage density, as well as apparatus configured to perform similar methods, might include determining whether a value of an indication of available power is less than a threshold, and, in response to determining that the value of the indication of available power is less than the threshold, increasing a size of the first pool of memory cells, limiting write operations of the memory to the first pool of memory cells, and postponing movement of data from the first pool of memory cells to the second pool of memory cells.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Avani F. Trivedi, Tracy D. Evans, Carla L. Christensen, Tomoko Ogura Iwasaki, Aparna U. Limaye
  • Publication number: 20210065820
    Abstract: Methods of operating a memory having a first pool of memory cells having a first storage density and a second pool of memory cells having a second storage density greater than the first storage density, as well as apparatus configured to perform similar methods, might include determining whether a value of an indication of available power is less than a threshold, and, in response to determining that the value of the indication of available power is less than the threshold, increasing a size of the first pool of memory cells, limiting write operations of the memory to the first pool of memory cells, and postponing movement of data from the first pool of memory cells to the second pool of memory cells.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Avani F. Trivedi, Tracy D. Evans, Carla L. Christensen, Tomoko Ogura Iwasaki, Aparna U. Limaye
  • Publication number: 20210064265
    Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a criticality value can be determined and used as a basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a criticality value associated with performing a garbage collection operation satisfies a condition. Based on determining that the condition is satisfied, a parameter associated with performing the garbage collection operation can be adjusted. The garbage collection operation is performed on the data block stored on the memory component using the adjusted parameter.
    Type: Application
    Filed: August 17, 2020
    Publication date: March 4, 2021
    Inventors: Jianmin Huang, Aparna U. Limaye, Avani F. Trivedi, Tomoko Ogura Iwasaki, Tracy D. Evans
  • Publication number: 20210055990
    Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a signaling can be received that indicates a request from a controller to migrate valid data from a first data block to a second data block. For example, the first data block can be a data block of a plurality of memory cells configured as single-level-cell (SLC) memory. The second data block can be configured as multi-level-cell (MLC) memory. The data migration operation can include an error control operation that is performed using the memory component, the error control operation excluding transferring the data to the controller. The data can be migrated from the first data block configured as SLC memory to the second data block configured as MLC memory after the error control operation is performed using the memory component.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Inventors: Tomoko Ogura Iwasaki, Avani F. Trivedi, Jianmin Huang, Aparna U. Limaye, Tracy D. Evans
  • Publication number: 20210056019
    Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a battery state associated with the memory system or sub-system may be used as an indicator or basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a battery state or condition satisfies a criterion. Based on determining that the criterion is satisfied the, the garbage collection operation may be postponed until the battery state changes to satisfy a different battery condition.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Inventors: Aparna U. Limaye, Tracy D. Evans, Tomoko Ogura Iwasaki, Avani F. Trivedi, Jianmin Huang
  • Publication number: 20210057018
    Abstract: Systems and methods for read operations and management are disclosed. More specifically, this disclosure is directed to receiving a first read command directed to a first logical address and receiving, after the first read command, a second read command directed to a second logic address. The method also includes receiving, after the second read command, a third read command directed to a third logical address and determining that the first logical address and the third logical address correspond to a first physical address and a third physical address, respectively. The first physical address and the third physical address can be associated with a first word line of a memory component while the second logical address corresponds to a second physical address associated with a second word line of the memory component. The method includes executing the first read command and the third read command sequentially.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Inventors: Tomoko Ogura Iwasaki, Tracy D. Evans, Avani F. Trivedi, Aparna U. Limaye, Jianmin Huang
  • Publication number: 20210055878
    Abstract: Systems, apparatuses, and methods related to data compaction in memory or storage systems or sub-systems, such as solid state drives, are described. For example, one or more memory pages storing valid data can be identified from a first data block in a plane of a memory component and copied to a page buffer corresponding to the plane. A controller of the system or sub-system can determine whether the plane of the memory component has another data block with capacity to store the one or more memory pages and can copy the one or more memory pages from the page buffer either to the other data block or to a different data block in a different plane of the memory component.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Inventors: Tomoko Ogura Iwasaki, Avani F. Trivedi, Aparna U. Limaye, Jianmin Huang, Tracy D. Evans
  • Patent number: 8710576
    Abstract: A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: April 29, 2014
    Assignee: Halo LSI Inc.
    Inventors: Seiki Ogura, Tomoko Ogura Iwasaki, Nori Ogura
  • Publication number: 20090200603
    Abstract: A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories. Array implementations for high-density memory arrays and high-speed memory arrays and their fabrication methods are also described.
    Type: Application
    Filed: February 11, 2009
    Publication date: August 13, 2009
    Inventors: Seiki Ogura, Tomoko Ogura Iwasaki, Nori Ogura