Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a battery state associated with the memory system or sub-system may be used as an indicator or basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a battery state or condition satisfies a criterion. Based on determining that the criterion is satisfied the, the garbage collection operation may be postponed until the battery state changes to satisfy a different battery condition.

Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a signaling can be received that indicates a request from a controller to migrate valid data from a first data block to a second data block. For example, the first data block can be a data block of a plurality of memory cells configured as single-level-cell (SLC) memory. The second data block can be configured as multi-level-cell (MLC) memory. The data migration operation can include an error control operation that is performed using the memory component, the error control operation excluding transferring the data to the controller. The data can be migrated from the first data block configured as SLC memory to the second data block configured as MLC memory after the error control operation is performed using the memory component.

Abstract: Some embodiments include an assembly having channel-material-structures, and having memory cells along the channel-material-structures. The memory cells include charge-storage-material. Linear-conductive-structures are vertically offset from the channel-material-structures and are electrically coupled with the channel-material-structures. Intervening regions are between the linear-conductive-structures. Conductive-shield-structures are within the intervening regions. The conductive-shield-structures are electrically coupled with a reference-voltage-source.

Abstract: Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

Abstract: Systems, apparatuses, and methods related to media management, including “garbage collection,” in memory or storage systems or sub-systems, such as solid state drives, are described. For example, a criticality value can be determined and used as a basis for managing a garbage collection operation on a data block. A controller or the system or sub-system may determine that a criticality value associated with performing a garbage collection operation satisfies a condition. Based on determining that the condition is satisfied, a parameter associated with performing the garbage collection operation can be adjusted. The garbage collection operation is performed on the data block stored on the memory component using the adjusted parameter.

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

Abstract: Control logic in a memory device cause a programming pulse to be applied to a set of wordlines including a first set of even-numbered wordlines corresponding to a first set of memory cells to be erased and a second set of odd-numbered wordlines corresponding to a second set of memory cells to be erased, where a set of electrons are injected into a first set of gate regions, a second set of gate regions, and a set of inter-cell regions of a charge trap (CT) layer of the memory device. The control logic executes a first erase cycle on the first set of even-numbered wordlines to remove a first subset of electrons from the first set of gate regions corresponding to the first set of even-numbered wordlines. The control logic executes a second erase cycle on the second set of odd-numbered wordlines to remove a second subset of electrons from the second set of gate regions corresponding to the second set of even-numbered wordlines.

Abstract: Control logic in a memory device causes a boost voltage to be applied one or more times to a plurality of unselected wordlines of a block of the memory array, the block comprising a plurality of sub-blocks, and the boost voltage to boost a channel potential of each of the plurality of sub-blocks by an amount each time the boost voltage is applied. The control logic further selectively discharges the amount of boost voltage from one or more of the plurality of sub-blocks after each time the boost voltage is applied according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. Additionally, the control logic causes a single programming pulse to be applied to one or more selected wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

Abstract: A memory device comprises a substrate and a memory array disposed above the substrate, the memory array comprising a plurality of vertically stacked layers, each vertically stacked layer comprising a plurality of word lines. The memory device further comprises a plurality of vertical string driver circuits disposed above the memory array, wherein each of the plurality of vertical string driver circuits comprises one or more semiconductor devices coupled to a respective one of the plurality of word lines.

Abstract: Memories having a first pool of memory cells having a first storage density and a second pool of memory cells having a second storage density greater than the first storage density, and a controller configured to cause the memory to determine whether a value of an indication of available power of a power supply for the memory is less than a threshold, and in response to determining that the value of the indication of available power is less than the threshold, increase a size of the first pool of memory cells, limit programming of data received by the memory to the first pool of memory cells, and cease movement of data from the first pool of memory cells to the second pool of memory cells, as well as apparatus including similar memories.

Abstract: Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.

Abstract: A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a representation of the input search word and a representation of an inverse of the input search word. The search pattern is provided as input to search lines of a ternary content-addressable memory (TCAM) block. A subset of the search lines is set to a logical high state based on a first portion of the input search word being designated as don't-care bits. The search pattern causes at least one string in the CAM block to be conductive and provide a signal in response to a data entry stored on the string comprising a second portion of the input search word that excludes the don't-care bits. A location of the data entry is determined and output.

Abstract: Control logic in a memory device identifies a set of memory cells in a block of a memory array, wherein the set of memory cells comprises two or more memory cells programmed during a program phase of a program operation and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a program verify phase of the program operation and performs concurrent sensing operations on the set of memory cells to determine whether each memory cell in the set of memory cells was programmed to at least the program verify voltage during the program phase of the program operation.

Abstract: A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

Abstract: A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, wordlines coupled with first and second pillars. Control logic is to cause: wordlines to be discharged after a program pulse is applied to selected wordline; a supply voltage be applied to second data line to cause a voltage of second pillar to float; a ground voltage be applied to first data line to inhibit soft erase via first pillar; unselected wordlines be charged to boost channel voltages in memory cells coupled with the second pillar; and one of the ground voltage or a negative voltage be applied to the selected wordline to increase soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline, causing a threshold voltage stored in the memory cell to be erased.

Abstract: An access request is received. The access request comprises a physical page address corresponding to a primary memory block of a memory device, an input security key, and a logical page address corresponding to the physical page address. The input security key is provided as input to a (CAM) block that stores a plurality of security keys to verify that the input security key matches a stored security key. A location of the stored security key is checked to verify that it corresponds to the logical page address included in the access request based a predetermined mapping. Based on verifying that the stored security key corresponds to the logical page address included in the access request, the physical page address corresponding to the primary memory block is accessed.

Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.

Abstract: Methods and devices related to a cellular signal mesh network are described. In an example, a method can include determining, via a processing resource of a first computing device, whether a cellular signal of the first computing device is below a threshold cellular signal, transmitting from the first computing device to a second computing device first signaling including data representing a request for operational data of the second computing device in response to determining that the cellular signal of the first computing device is below the threshold cellular signal, receiving from the second computing device second signaling comprising the operational data of the second computing device, and transmitting from the first computing device to the second computing device third signaling including data representing at least one of: a voice call, a video call, or a message in response to receiving the second signaling comprising the operational data.