Patents by Inventor Tomoko Tamura

Tomoko Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210331247
    Abstract: A method of producing an additively manufactured object comprises: a step of cooling a shaped body of an alloy formed by additive manufacturing to 0° C. or lower; and a step of aging the shaped body under a temperature condition of 400° C. or higher and 600° C. or lower after the step of cooling the shaped body. The alloy contains: Fe as a main component; 17.0 mass % or more and 19.0 mass % or less of Ni; 7.0 mass % or more and 12.5 mass % or less of Co; 4.6 mass % or more and 5.2 mass % or less of Mo; 0.13 mass % or more and 1.6 mass % or less of Ti; and 0.05 mass % or more and 0.15 mass % or less of Al.
    Type: Application
    Filed: April 20, 2021
    Publication date: October 28, 2021
    Inventors: Takahiro TACHIBANA, Noriyuki HIRAMATSU, Tomoko TAMURA
  • Publication number: 20210040594
    Abstract: A method of manufacturing a metal member, includes shaping a metal member configured of Ni-based alloy by an additive manufacturing; and carrying a solution treatment to the metal member. In the solution treatment, a heat treatment is carried out at a temperature in a temperature range of (TC?100)° C. to (TC?50)° C. (TC is a solid solution temperature of Ni-based alloy). In this way, a creep characteristic and a low cycle fatigue characteristic have been secured sufficient in the metal member shaped by the additive manufacturing.
    Type: Application
    Filed: May 8, 2017
    Publication date: February 11, 2021
    Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Tomoko TAMURA, Noriyuki HIRAMATSU, Kiyokatsu SAKAKIBARA
  • Publication number: 20180135186
    Abstract: An oxide film removing method is a method of removing an oxide film formed in a surface of a superalloy part that contains a first metal as a base metal and a second metal different from the first metal. The oxide film removing method includes arranging the superalloy part inside a heating chamber; reducing the oxide of the base metal to the base metal by heating the inside of the heating chamber in a condition that a reduction gas atmosphere or a vacuum atmosphere is maintained; and carrying out acid processing to apply acid solution to the superalloy part after the reduction. The oxide film formed in the surface of the superalloy is removed effectively without using a highly toxic gaseous fluoride.
    Type: Application
    Filed: April 27, 2016
    Publication date: May 17, 2018
    Inventors: Wataru SASAKI, Tomoko TAMURA, Noriyuki HIRAMATSU, Osamu MORII
  • Patent number: 9941115
    Abstract: A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: April 10, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoko Tamura, Eiji Sugiyama, Yoshitaka Dozen, Koji Dairiki, Takuya Tsurume
  • Publication number: 20150049900
    Abstract: A system capable of providing information having a large amount of data without spoiling the aesthetic appearance of an object is provided. An information provision terminal device 8 which has received an address corresponding code transmits the address corresponding code to a video transmission device 12 of a broadcasting station. The video transmission device 12 embeds the received address corresponding code as a digital watermark in video to generate a broadcast program (broadcast contents) and transmits the broadcast program. An information address acquisition means 24 transmits the extracted address corresponding code to a management server device 4. An information address transmission means 44 of the management server device 4 reads an information address recorded with the address corresponding code from a recording unit 42 and transmits the information address by return to an information reception terminal device 2.
    Type: Application
    Filed: January 25, 2013
    Publication date: February 19, 2015
    Inventors: Motoki Kamitani, Masahiko Mano, Tomoko Tamura
  • Patent number: 8790994
    Abstract: It is an object of the present invention to reduce the cost of a wireless chip, further, to reduce the cost of a wireless chip by enabling the mass production of a wireless chip, and furthermore, to provide a downsized and lightweight wireless chip. A wireless chip in which a thin film integrated circuit peeled from a glass substrate or a quartz substrate is formed between a first base material and a second base material is provided according to the invention. As compared with a wireless chip formed from a silicon substrate, the wireless chip according to the invention realizes downsizing, thinness, and lightweight. The thin film integrated circuit included in the wireless chip according to the invention at least has an n-type thin film transistor having an LDD (Lightly Doped Drain) structure, a p-type thin film transistor having a single drain structure, and a conductive layer functioning as an antenna.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: July 29, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Junya Maruyama, Tomoko Tamura, Eiji Sugiyama, Yoshitaka Dozen
  • Publication number: 20130323912
    Abstract: A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.
    Type: Application
    Filed: July 25, 2013
    Publication date: December 5, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoko TAMURA, Eiji SUGIYAMA, Yoshitaka DOZEN, Koji DAIRIKI, Takuya TSURUME
  • Patent number: 8530335
    Abstract: A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: September 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoko Tamura, Eiji Sugiyama, Yoshitaka Dozen, Koji Dairiki, Takuya Tsurume
  • Publication number: 20120322212
    Abstract: It is an object of the present invention to reduce the cost of a wireless chip, further, to reduce the cost of a wireless chip by enabling the mass production of a wireless chip, and furthermore, to provide a downsized and lightweight wireless chip. A wireless chip in which a thin film integrated circuit peeled from a glass substrate or a quartz substrate is formed between a first base material and a second base material is provided according to the invention. As compared with a wireless chip formed from a silicon substrate, the wireless chip according to the invention realizes downsizing, thinness, and lightweight. The thin film integrated circuit included in the wireless chip according to the invention at least has an n-type thin film transistor having an LDD (Lightly Doped Drain) structure, a p-type thin film transistor having a single drain structure, and a conductive layer functioning as an antenna.
    Type: Application
    Filed: August 28, 2012
    Publication date: December 20, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Koji DAIRIKI, Junya MARUYAMA, Tomoko TAMURA, Eiji SUGIYAMA, Yoshitaka DOZEN
  • Patent number: 8288773
    Abstract: It is an object of the present invention to reduce the cost of a wireless chip, further, to reduce the cost of a wireless chip by enabling the mass production of a wireless chip, and furthermore, to provide a downsized and lightweight wireless chip. A wireless chip in which a thin film integrated circuit peeled from a glass substrate or a quartz substrate is formed between a first base material and a second base material is provided according to the invention. As compared with a wireless chip formed from a silicon substrate, the wireless chip according to the invention realizes downsizing, thinness, and lightweight. The thin film integrated circuit included in the wireless chip according to the invention at least has an n-type thin film transistor having an LDD (Lightly Doped Drain) structure, a p-type thin film transistor having a single drain structure, and a conductive layer functioning as an antenna.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: October 16, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Junya Maruyama, Tomoko Tamura, Eiji Sugiyama, Yoshitaka Dozen
  • Patent number: 8236629
    Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: August 7, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Dozen, Tomoko Tamura, Takuya Tsurume, Koji Dairiki
  • Patent number: 8030132
    Abstract: To simplify a peeling step in a method for manufacturing a semiconductor device including the peeling step. A first layer having a metal film is formed over a substrate; a second layer having a transistor is formed over the first layer having the metal film; a resin material is applied over the layer having the transistor; the resin material is cured by a heat treatment at a first heat treatment temperature to form a resin layer; the layer having the transistor is peeled from the substrate by a heat treatment at a second heat treatment temperature which is higher than the first heat treatment temperature; and the resin layer is peeled from the layer having the transistor by a heat treatment at a third heat treatment temperature which is higher than the second heat treatment temperature.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: October 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kaori Ogita, Tomoko Tamura
  • Publication number: 20110207292
    Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time.
    Type: Application
    Filed: May 4, 2011
    Publication date: August 25, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yoshitaka DOZEN, Tomoko TAMURA, Takuya TSURUME, Koji DAIRIKI
  • Publication number: 20110198543
    Abstract: Upon dispersing fine carbon fibers into water, by using an anionic surfactant having a high electrostatic repulsion effect, an nonionic surfactant having a high stereoscopic repulsion effect, and an anionic surfactant having high electrostatic and stereoscopic repulsion effects, in combination, an aqueous dispersion of fine carbon fibers which shows a high dispersibility without causing significant cohesion of mutual fine carbon fibers, and maintains a mean particle diameter (d50) of not more than 350 nm in a wide concentration range from a relatively low concentration to a relatively high concentration is provided.
    Type: Application
    Filed: October 9, 2009
    Publication date: August 18, 2011
    Applicant: HODOGAYA CHEMICAL CO., LTD.,
    Inventors: Naohiro Tarumoto, Tomoko Tamura, Takayuki Tsukada
  • Publication number: 20110171778
    Abstract: A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.
    Type: Application
    Filed: March 25, 2011
    Publication date: July 14, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tomoko TAMURA, Eiji SUGIYAMA, Yoshitaka DOZEN, Koji DAIRIKI, Takuya TSURUME
  • Patent number: 7939385
    Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. A feature of the invention is to use a metal film and a reactant having the metal film as a separation layer. An etching rate of the metal film or the reactant having metal is high, and a physical means in addition to a chemical means of etching the metal film or the reactant having metal can be used in the invention. Thus, the IDF chip can be manufactured more simply and easily in a short time.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: May 10, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Dozen, Tomoko Tamura, Takuya Tsurume, Koji Dairiki
  • Patent number: 7927971
    Abstract: A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: April 19, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoko Tamura, Eiji Sugiyama, Yoshitaka Dozen, Koji Dairiki, Takuya Tsurume
  • Patent number: 7875530
    Abstract: First semiconductor integrated circuits and second semiconductor integrated circuits arranged over a first substrate so that each of the second semiconductor integrated circuits is adjacent to one of the first semiconductor integrated circuits are transferred to additional substrates through multiple transfer operations. After the first semiconductor integrated circuits and the second semiconductor integrated circuits formed over the first substrate are transferred to the additional substrates (a fourth substrate and a fifth substrate) respectively, the circuits are divided into a semiconductor device corresponding to each semiconductor integrated circuit. The first semiconductor integrated circuits are arranged while keeping a distance from each other over the fourth substrate, and the second semiconductor integrated circuits are arranged while keeping a distance from each other over the fifth substrate. Thus, a large division margin of each of the fourth substrate and the fifth substrate can be obtained.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: January 25, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoko Tamura, Tomoyuki Aoki, Takuya Tsurume, Koji Dairiki
  • Patent number: 7704765
    Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device, capable of keeping a peeling layer from being peeled from a substrate in the phase before the completion of a semiconductor element and peeling a semiconductor element rapidly. It is considered that a peeling layer tends to be peeled from a substrate because the stress is applied to a peeling layer due to the difference in thermal expansion coefficient between a substrate and a peeling layer, or because the volume of a peeling layer is reduced and thus the stress is applied thereto by crystallization of the peeling layer due to heat treatment. Therefore, according to one feature of the invention, the adhesion of a substrate and a peeling layer is enhanced by forming an insulating film (buffer film) for relieving the stress on the peeling layer between the substrate and the peeling layer before forming the peeling layer over the substrate.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: April 27, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventors: Junya Maruyama, Atsuo Isobe, Susumu Okazaki, Koichiro Tanaka, Yoshiaki Yamamoto, Koji Dairiki, Tomoko Tamura
  • Patent number: 7588969
    Abstract: The present invention provides a manufacturing method of a thinned semiconductor device with high reliability at low cost and a semiconductor device manufactured by the method. A peeling layer, a transistor, and an insulating layer are formed in this order over a substrate, an opening is formed so as to expose at least a part of the peeling layer, and the transistor is peeled off from the substrate by a physical means. The peeling layer is formed by forming a metal film and a metal oxide film so as to be in contact with the metal film by a method using a solution.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: September 15, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kaori Ogita, Tomoko Tamura, Junya Maruyama, Koji Dairiki