Abstract: A data processing system includes a satellite storage device communicating with a central storage device via a network. The satellite storage device is capable of accessing the data of the central storage device and includes a storage unit capable of storing data duplicated from the central storage device. The satellite storage device is capable of selecting a synchronization policy which determines how to synchronize data between the storage unit and of the central storage device.

Abstract: A network switch fabric is provided for a clustering system to facilitate flexibility of network-related interconnection selection and system scalability. The network switch fabric includes replaceable network switch(s) and network interface(s) selectively configured on a base board. Multiple types of interconnection protocols with similar characteristics will be able to implement on a common infrastructure of network switch fabric. A pass through card operating as a network interface is also applicable on the network switch fabric to directly connect with an external network. The pass through card allows the network switch fabric supporting the clustering system to be scalable, thereby capable of supporting a large-scale cluster computing.

Abstract: A clocking scheme is provided to synchronize system clock across plural independent SMP (Symmetric Multi-Processing) domains of the multi-processor system. Each of the SMP domains is connected with another through an interconnection board and two or more identical connectors. The clocking scheme includes a clock source, a SPLL (Select Phase-Locked Loop) and a clock buffer on each of the SMP domains to provide a dedicated base clock. A self-clock path is used to send the base clock from the clock source to the SPLL on the same SMP domain, and on the other hand one or more base clock is sent through a distribution-clock path to another SPLL. The distribution-clock path and the self-clock path will have equal lengths, making the base clock pass through the two connectors or the same connector twice to achieve the similar electrical characteristics and balance the skew or propagation delay.

Abstract: A data processing system includes a satellite storage device communicating with a central storage device via a network. The satellite storage device is capable of accessing the data of the central storage device and includes a storage unit capable of storing data duplicated from the central storage device. The satellite storage device is capable of selecting a synchronization policy which determines how to synchronize data between the storage unit and of the central storage device.

Abstract: A power supply system includes a function unit, a power supply unit, a power distributing unit, and a capacitor. The power supply unit includes at least one first power supply module supplying voltage to the function unit and at least one second power supply module supply voltage to the function unit only when the at least one first power supply module is not supplying a voltage. The power distributing unit electrically couples the function unit with the power supply unit. The power supply unit is capable of supplying voltage to the function unit via the power distributing unit. The capacitor is electrically coupled to the function unit in parallel and capable of supplying voltage to the function unit when the power supply unit cannot supply the voltage to the function unit.

Abstract: A client management system includes a client terminal capable of communicating with a server terminal. The client terminal includes a storage device and a security managing module. The storage device is capable of storing data checked out data from the server terminal. The security managing module is capable of deleting the checked-out data in the storage device when a checked-out period determined by the server terminal has expired.

Abstract: A physical hardware architecture is provided to fulfill flexibility, serviceability and configurability of a multi-processor system. The architecture mainly includes a bottom plane, plural processor boards and a function board. On the front section of the top side of the bottom plane, the processor boards are configured thereon. The function board faces downwards and is configured in an edge-to-edge connection with the front edge of the bottom plane. Function card(s) may be configured vertically on the bottom surface of the function board. On the rear section of the top side of the bottom plane expansion card(s) are configured vertically. With main system fan(s) located on the top of the function board and auxiliary system fan configured under the bottom plane, the multi-processor system will also achieve optimum cooling capability through the architecture.

Abstract: A remote monitor module for power initialization of a computer system includes a monitor logic and a BMC (Baseboard Management Controller). The monitor logic is in circuit connection with a power-up sequence controller and several basic voltage domains on a system board of the computer system. The monitor logic also defines a monitor power-up sequence to perform a basic power-up sequence defined in the power-up sequence controller and allow system changes in power initialization. Extra voltage domain(s) may be enabled and monitored according to the monitor power-up sequence. Eventually, multiple power initialization event/state signals are transmitted by the monitor logic to a remote management host through the BMC.

Abstract: A scalable computer system includes a reconfigurable chassis module, plural hardware units and one or more inter-plane. The chassis module has plural modular units for configuring the hardware units therein respectively. Each of the modular units has dedicated framework to attach the inter-plane or dedicated fans. The inter-plane is to connect with the separated hardware units between the modular units. Each of the modular units is equipped with compatible male and female joints to engage with each other. Certain fastening assemblies may be applied to secure male-male or female-female joints, thereby enabling the modular units to be front-to-back and/or side-by-side connections.

Abstract: A symmetric multiprocessor computer is provided with a star interconnection architecture and a cooling system. The star interconnection architecture include a middle plane, and plural first processor boards and second processor boards configured vertically onto opposite surfaces of the middle plane. The first processor boards and the second processor boards are crisscross to each other at the opposite surfaces of the middle plane. The cooling system includes a first cooling module and a second cooling system module configured for generating a plurality of first airflows and second airflows for the first processor boards and the second processor boards respectively, wherein the paths of the first airflows and the second airflows are crisscross to each other at the opposite surfaces of the middle plane.

Abstract: A network switch fabric is provided for a clustering system to facilitate flexibility of network-related interconnection selection and system scalability. The network switch fabric includes replaceable network switch(s) and network interface(s) selectively configured on a base board. Multiple types of interconnection protocols with similar characteristics will be able to implement on a common infrastructure of network switch fabric. A pass through card operating as a network interface is also applicable on the network switch fabric to directly connect with an external network. The pass through card allows the network switch fabric supporting the clustering system to be scalable, thereby capable of supporting a large-scale cluster computing.

Abstract: A symmetric multiprocessor computer is provided with a star interconnection architecture and a cooling system. The star interconnection architecture include a middle plane, and plural first processor boards and second processor boards configured vertically onto opposite surfaces of the middle plane. The first processor boards and the second processor boards are crisscross to each other at the opposite surfaces of the middle plane. The cooling system includes a first cooling module and a second cooling system module configured for generating a plurality of first airflows and second airflows for the first processor boards and the second processor boards respectively, wherein the paths of the first airflows and the second airflows are crisscross to each other at the opposite surfaces of the middle plane.

Abstract: A three dimensional interconnection architecture is provided for a multiprocessor computer. The interconnection architecture includes multiple processor boards, one or more interconnection board and one or more edge board. The processor boards are configured parallel to each other, each having plural processors configured thereon. The interconnection board is connected with one side of each of the processor boards to allow one of the processors on one of the processor boards operatively connecting with another one of the processors on another one of the processor boards. The edge board is connected with another side of each of the processor boards to allow one of the processors on one of the processor boards operatively connecting with another one of the processors on another one of the processor boards.

Abstract: A system is provided to assign IP (Internet Protocol) addresses to plural management modules under different IP modes. The system management modules are configured in a computing system that is integrated in a single chassis. All the system management modules are connected through a first management network to be assigned with a static IP address or a DHCP. Besides, a secondary system management network is used for each of the management modules to facilitate the assignment of pre-assigned private IP addresses based on the board IDs of the management modules. When DHCP mode is selected, IP configuration will be performed automatically. Namely in DHCP mode, even if the system is disconnected from the external network, the system management can be done through the system management network with the pre-assigned private IP address.

Abstract: An interconnection architecture is provided for flexibly connecting a primary host module or an added host module to a network switch in a clustering system. The interconnection architecture mainly includes plural first slots, a primary function module, an added function module and plural multifunctional buses. The first slots electrically connect the network switch with the primary and added host modules. The primary function module inserts in one of the first slots to electrically connect the primary host module with the network switch; and the added function module inserts in one of the first slots to electrically connect the added host module with the network switch. The multifunctional buses connect the network switch with the first slots and also connect the first slots with the primary host module and the added host module.

Abstract: A system and a method are provided for assigning plural identity addresses in sequence from a central management module to plural corresponding local management modules. A standby power is input to a current one of the local management modules. And the standby power towards a next un-actuated one of the local management modules is delayed for a delay period. Thus, the current one of the local management modules is allowed negotiating for assigning a dedicated one of the identity addresses.

Abstract: A fan control architecture is provided for controlling system fan(s) on a computing system that has multiple nodes, a system management network and a fan control module. On each of the nodes a management module is configured to collect system information thereon. In a main fan control scheme, a system management node controls the system fan through the fan control module according to the temperature data sent back from the management module of the other nodes through the system management network. The fan control scheme includes redundant path(s) connected between all the nodes and the fan control module to send high-temperature signals to the fan control module directly. In the case that a threshold high temperature is reached, the fan control module will set the system fan at a predetermined high speed according to the high-temperature signals.

Abstract: A physical hardware architecture is provided to fulfill flexibility, serviceability and configurability of a multi-processor system. The architecture mainly includes a bottom plane, plural processor boards and a function board. On the front section of the top side of the bottom plane, the processor boards are configured thereon. The function board faces downwards and is configured in an edge-to-edge connection with the front edge of the bottom plane. Function card(s) may be configured vertically on the bottom surface of the function board. On the rear section of the top side of the bottom plane expansion card(s) are configured vertically. With main system fan(s) located on the top of the function board and auxiliary system fan configured under the bottom plane, the multi-processor system will also achieve optimum cooling capability through the architecture.

Abstract: A clocking scheme is provided to synchronize system clock across plural independent SMP (Symmetric Multi-Processing) domains of the multi-processor system. Each of the SMP domains is connected with another through an interconnection board and two or more identical connectors. The clocking scheme includes a clock source, a SPLL (Select Phase-Locked Loop) and a clock buffer on each of the SMP domains to provide a dedicated base clock. A self-clock path is used to send the base clock from the clock source to the SPLL on the same SMP domain, and on the other hand one or more base clock is sent through a distribution-clock path to another SPLL.

Abstract: A system management architecture is provided to manage plural compute nodes in a clustering system. Each of the compute nodes basically includes a BMC (Baseboard Management Controller) for local management. Among the compute nodes, a preset one has its BMC connecting with a management network switch through an extra network interface for clustering/system management. A first network interface, which is usually used to connect with the management network switch for communicating with other compute nodes, is utilized for the BMC of the preset compute node to connect with an external management host. A chipset on the preset compute node also connects with the external management host through a system I/O bus and the first network interface. On the preset compute node a operating system provides Network Address Translation service to allow the external management host to access each of the compute nodes.