Patents by Inventor Tomonori Hirai

Tomonori Hirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080046774
    Abstract: A redundant clock distribution architecture is provided for a blade clustering system to achieve SMP (symmetric multi-processor) capability and flexible system configuration. The architecture mainly provides a central clock signal from a central clock and a local clock signal from an operative local clock configured on each blade module of the system. A clock multiplexer selects the central clock signal and sends to plural local clock consumers on each blade module. The clock multiplexer switches to send the local clock signal if the central clock fails.
    Type: Application
    Filed: October 31, 2006
    Publication date: February 21, 2008
    Applicant: Tyan Computer Corporation
    Inventors: Tomonori Hirai, Jyh Ming Jong
  • Publication number: 20080043405
    Abstract: A chassis partition architecture of a chassis for configuring a multi-processor system is provided to fulfill flexibility, serviceability and configurability of a multi-processor system. The partition architecture mainly includes the partition architecture mainly includes a node partition, a expansion partition and a function partition. The node partition is located at a middle section of the chassis, mainly for containing several processor boards that are configured vertically and lengthwise. The expansion partition is located behind the node partition, mainly for containing several expansion boards that are configured vertically and lengthwise. And the function partition is located at a front section of the chassis lower than the node partition and the expansion partition, mainly for containing a plurality of function cards that are configured upside-down vertically and lengthwise.
    Type: Application
    Filed: March 16, 2007
    Publication date: February 21, 2008
    Applicant: TYAN COMPUTER CORPORATION
    Inventors: Mario J.D. LEE, Tomonori HIRAI, Jyh Ming JONG
  • Publication number: 20080043427
    Abstract: A scalable computer system includes a reconfigurable chassis module, plural hardware units and one or more inter-plane. The chassis module has plural modular units for configuring the hardware units therein respectively. Each of the modular units has dedicated framework to attach the inter-plane or dedicated fans. The inter-plane is to connect with the separated hardware units between the modular units. Each of the modular units is equipped with compatible male and female joints to engage with each other. Certain fastening assemblies may be applied to secure male-male or female-female joints, thereby enabling the modular units to be front-to-back and/or side-by-side connections.
    Type: Application
    Filed: October 30, 2006
    Publication date: February 21, 2008
    Applicant: TYAN COMPUTER CORPORATION
    Inventors: Mario J.D. Lee, Tomonori Hirai, Jyh Ming Jong
  • Publication number: 20080046707
    Abstract: A remote monitor module for power initialization of a computer system includes a monitor logic and a BMC (Baseboard Management Controller). The monitor logic is in circuit connection with a power-up sequence controller and several basic voltage domains on a system board of the computer system. The monitor logic also defines a monitor power-up sequence to perform a basic power-up sequence defined in the power-up sequence controller and allow system changes in power initialization. Extra voltage domain(s) may be enabled and monitored according to the monitor power-up sequence. Eventually, multiple power initialization event/state signals are transmitted by the monitor logic to a remote management host through the BMC.
    Type: Application
    Filed: December 6, 2006
    Publication date: February 21, 2008
    Applicant: TYAN COMPUTER CORPORATION
    Inventors: Tomonori Hirai, Jyh Ming Jong
  • Publication number: 20080046705
    Abstract: A system and method are provided to enable flexible symmetric multi-processor (SMP) configuration. The system includes plural bootable domains and a glue logic. The bootable domains include plural processors, one or more boot image and one or more bridge interface. Each of the bootable domains links to another through the connection between the processors. The glue logic receives and processes a configuration signal and generates enable/disable signals to enable/disable each of the bootable domains and define one or more actual boot domain. The processor of the enabled bootable domain initializes the dedicated actual boot domain by accessing boot instructions from the boot image through the bridge interface.
    Type: Application
    Filed: October 6, 2006
    Publication date: February 21, 2008
    Applicant: TYAN COMPUTER CORPORATION
    Inventors: Tomonori Hirai, Jyh Ming Jong
  • Publication number: 20080046706
    Abstract: A remote monitor module is provided to monitor initialization events of a computer host domain on a local mainboard. The remote module includes an event monitor to detect certain initialization events during system initialization process, and then generates and transmits event signals to a BMC (Baseboard Management Controller). A decoder may be used to decode BIOS check data at a specific I/O address and provides check data signals to the BMC. The BMC receives the event signals and/or the check data signals and transmits to a remote management host through remote management link(s).
    Type: Application
    Filed: October 31, 2006
    Publication date: February 21, 2008
    Applicant: TYAN COMPUTER CORPORATION
    Inventors: Tomonori Hirai, Jyh Ming Jong
  • Patent number: 6447309
    Abstract: An apparatus for suppressing power bus bouncing in a hot-swappable system has been developed. The apparatus includes a connection module with three interior pins for: the power return; the power supply; and the system ground. The system ground pin is shorter than the other two so that it makes contact with the power bus after the bouncing from the return and supply pins has subsided.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: September 10, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Han Y. Ko, Robert C. Cyphers, Tomonori Hirai, Keith Y. Oka, Alan D. Martin
  • Publication number: 20020072259
    Abstract: An apparatus for suppressing power bus bouncing in a hot-swappable system has been developed. The apparatus includes a connection module with three interior pins for: the power return; the power supply; and the system ground. The system ground pin is shorter than the other two so that it makes contact with the power bus after the bouncing from the return and supply pins has subsided.
    Type: Application
    Filed: December 12, 2000
    Publication date: June 13, 2002
    Inventors: Han Y. Ko, Robert C. Cyphers, Tomonori Hirai, Keith Y. Oka, Alan D. Martin