Patents by Inventor Tomonori Kurosawa
Tomonori Kurosawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869593Abstract: According to an embodiment, a semiconductor memory device includes a memory cell, a first word line coupled between a control end of the memory cell and a first node, a resistance element coupled between the first node and a second node, a control circuit configured to output a voltage to the second node, a first switch coupled between the first node and a third node, a second switch coupled between the second node and the third node, and a comparator including an input end that receives a signal corresponding to a voltage of the third node.Type: GrantFiled: January 14, 2022Date of Patent: January 9, 2024Assignee: Kioxia CorporationInventors: Katsuaki Sakurai, Osamu Kobayashi, Tomonori Kurosawa
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Patent number: 11815925Abstract: A power source circuit includes: a plurality of power supply circuits which are electrically connected to different positions in a power supply wiring through which power is supplied to a plurality of processing circuits, wherein each of the power supply circuits is configured to generate a power supply voltage with reference to an input reference voltage, and supply the power supply voltage to the power supply wiring; and a reference voltage supply circuit generate a plurality of reference voltages with different voltages and to each of the plurality of power supply circuits, supply one of the different reference voltages as the input reference voltage thereof.Type: GrantFiled: August 30, 2021Date of Patent: November 14, 2023Assignee: Kioxia CorporationInventor: Tomonori Kurosawa
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Publication number: 20220392531Abstract: According to an embodiment, a semiconductor memory device includes a memory cell, a first word line coupled between a control end of the memory cell and a first node, a resistance element coupled between the first node and a second node, a control circuit configured to output a voltage to the second node, a first switch coupled between the first node and a third node, a second switch coupled between the second node and the third node, and a comparator including an input end that receives a signal corresponding to a voltage of the third node.Type: ApplicationFiled: January 14, 2022Publication date: December 8, 2022Applicant: Kioxia CorporationInventors: Katsuaki SAKURAI, Osamu KOBAYASHI, Tomonori KUROSAWA
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Publication number: 20220269295Abstract: A power source circuit includes: a plurality of power supply circuits which are electrically connected to different positions in a power supply wiring through which power is supplied to a plurality of processing circuits, wherein each of the power supply circuits is configured to generate a power supply voltage with reference to an input reference voltage, and supply the power supply voltage to the power supply wiring; and a reference voltage supply circuit generate a plurality of reference voltages with different voltages and to each of the plurality of power supply circuits, supply one of the different reference voltages as the input reference voltage thereof.Type: ApplicationFiled: August 30, 2021Publication date: August 25, 2022Inventor: Tomonori KUROSAWA
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Patent number: 11209846Abstract: In one embodiment, a semiconductor device includes a reference voltage supply circuit configured to supply a first reference voltage and a second reference voltage. The device further includes a power source voltage supply circuit including a first power source voltage generator supplied with the first reference voltage and configured to generate a first power source voltage, and a second power source voltage generator supplied with the second reference voltage and configured to generate a second power source voltage, the power source voltage supply circuit being configured to supply the first power source voltage and the second power source voltage to a power source voltage line. The device further includes a voltage control circuit connected to the power source voltage line, and configured to control a value of the first reference voltage and a value the second reference voltage.Type: GrantFiled: July 29, 2020Date of Patent: December 28, 2021Assignee: KIOXIA CORPORATIONInventors: Kazuhiko Satou, Tomonori Kurosawa, Dai Nakamura
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Patent number: 11200951Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells; a first circuit configured to convert first data into second data relating to an order of thresholds of the memory cells; and a second circuit configured to perform a write operation on the memory cells based on the second data.Type: GrantFiled: September 5, 2019Date of Patent: December 14, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Rieko Funatsuki, Takahiko Sasaki, Tomonori Kurosawa
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Patent number: 11139039Abstract: According to one embodiment, a memory device includes a memory cell, a word line connected to the memory cell, a word line driver which generates a selection signal for the word line, a first transistor including a gate to which the selection signal generated by the word line driver is input, and a drain which supplies a signal based on the selection signal to the word line, and a detection circuit which detects a value based on a current flowing through the first transistor during a verification period after writing data to the memory cell.Type: GrantFiled: March 12, 2020Date of Patent: October 5, 2021Assignee: Kioxia CorporationInventors: Tomonori Kurosawa, Dai Nakamura
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Publication number: 20210080984Abstract: In one embodiment, a semiconductor device includes a reference voltage supply circuit configured to supply a first reference voltage and a second reference voltage. The device further includes a power source voltage supply circuit including a first power source voltage generator supplied with the first reference voltage and configured to generate a first power source voltage, and a second power source voltage generator supplied with the second reference voltage and configured to generate a second power source voltage, the power source voltage supply circuit being configured to supply the first power source voltage and the second power source voltage to a power source voltage line. The device further includes a voltage control circuit connected to the power source voltage line, and configured to control a value of the first reference voltage and a value the second reference voltage.Type: ApplicationFiled: July 29, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Kazuhiko SATOU, Tomonori KUROSAWA, Dai NAKAMURA
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Publication number: 20210057032Abstract: According to one embodiment, a memory device includes a memory cell, a word line connected to the memory cell, a word line driver which generates a selection signal for the word line, a first transistor including a gate to which the selection signal generated by the word line driver is input, and a drain which supplies a signal based on the selection signal to the word line, and a detection circuit which detects a value based on a current flowing through the first transistor during a verification period after writing data to the memory cell.Type: ApplicationFiled: March 12, 2020Publication date: February 25, 2021Applicant: Kioxia CorporationInventors: Tomonori KUROSAWA, Dai NAKAMURA
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Publication number: 20200185035Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells; a first circuit configured to convert first data into second data relating to an order of thresholds of the memory cells; and a second circuit configured to perform a write operation on the memory cells based on the second data.Type: ApplicationFiled: September 5, 2019Publication date: June 11, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Rieko FUNATSUKI, Takahiko Sasaki, Tomonori KUROSAWA
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Patent number: 10332593Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, first and second bit lines, a sense amplifier and a driver. The first and second memory cells have first and second threshold voltages, respectively. The word line is electrically connected to the first and second memory cells. The first and second bit lines are electrically connected to the first and second memory cells, respectively. The driver increases gradually the voltage of the word line. When the voltage of the word line is increased gradually by the driver, the sense amplifier senses the first and second threshold voltages in ascending order.Type: GrantFiled: December 16, 2016Date of Patent: June 25, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takahiko Sasaki, Go Shikata, Tomonori Kurosawa, Rieko Funatsuki
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Patent number: 10096356Abstract: According to one embodiment, a memory device includes a first memory cell; a second memory cell; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first word line connected to the first memory cell and the second memory cell; a first circuit configured to control a connection between the first bit line and a first node; and a second circuit configured to control a connection between the second bit line and the first node.Type: GrantFiled: March 9, 2016Date of Patent: October 9, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Koji Kato, Tomonori Kurosawa, Takeshi Nakano, Tsukasa Kobayashi
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Patent number: 9997570Abstract: A nonvolatile semiconductor memory device according to one embodiment includes: a first wiring extending in a first direction as a longitudinal direction thereof; a second wiring extending in a second direction as a longitudinal direction thereof, the second direction intersecting with the first direction; a memory cell disposed at an intersection portion of the first wiring and the second wiring, the memory cell including a variable resistive element; a select transistor having one end connected to the second wiring; and a third wiring connected to the other end of the select transistor. A semiconductor layer included in the select transistor has a first impurity concentration at the second end. An impurity concentration of the semiconductor layer decrease to a second impurity concentration from the first impurity concentration as approaching to the first end from the second end.Type: GrantFiled: December 22, 2016Date of Patent: June 12, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shuichi Toriyama, Tomonori Kurosawa
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Publication number: 20170271405Abstract: A nonvolatile semiconductor memory device according to one embodiment includes: a first wiring extending in a first direction as a longitudinal direction thereof; a second wiring extending in a second direction as a longitudinal direction thereof, the second direction intersecting with the first direction; a memory cell disposed at an intersection portion of the first wiring and the second wiring, the memory cell including a variable resistive element; a select transistor having one end connected to the second wiring; and a third wiring connected to the other end of the select transistor. A semiconductor layer included in the select transistor has a first impurity concentration at the second end. An impurity concentration of the semiconductor layer decrease to a second impurity concentration from the first impurity concentration as approaching to the first end from the second end.Type: ApplicationFiled: December 22, 2016Publication date: September 21, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shuichi TORIYAMA, Tomonori KUROSAWA
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Patent number: 9704584Abstract: A semiconductor memory device includes a first block including a first memory string that includes a first memory cell and a first select transistor, a second block including a second memory string that includes a second memory cell and a second select transistor, a source line that is connected to the first memory string and the second memory string, and a controller that applies a source line voltage to the source line and a first voltage to a gate of the second select transistor during a program operation in which data is written to the first memory cell, the first voltage being greater than ground voltage and less than or equal to the source line voltage.Type: GrantFiled: March 3, 2016Date of Patent: July 11, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Maejima, Yuya Suzuki, Hidehiro Shiga, Tomonori Kurosawa
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Publication number: 20170162257Abstract: According to one embodiment, a memory device includes a first memory cell; a second memory cell; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first word line connected to the first memory cell and the second memory cell; a first circuit configured to control a connection between the first bit line and a first node; and a second circuit configured to control a connection between the second bit line and the first node.Type: ApplicationFiled: March 9, 2016Publication date: June 8, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koji KATO, Tomonori KUROSAWA, Takeshi NAKANO, Tsukasa KOBAYASHI
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Publication number: 20170110186Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, first and second bit lines, a sense amplifier and a driver. The first and second memory cells have first and second threshold voltages, respectively. The word line is electrically connected to the first and second memory cells. The first and second bit lines are electrically connected to the first and second memory cells, respectively. The driver increases gradually the voltage of the word line. When the voltage of the word line is increased gradually by the driver, the sense amplifier senses the first and second threshold voltages in ascending order.Type: ApplicationFiled: December 16, 2016Publication date: April 20, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takahiko Sasaki, Go Shikata, Tomonori Kurosawa, Rieko Funatsuki
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Patent number: 9449691Abstract: A memory device includes a plurality of memory blocks, and a row decoder including a plurality of decoders including a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting another one of the memory blocks.Type: GrantFiled: September 16, 2015Date of Patent: September 20, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Koji Hosono, Tomonori Kurosawa
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Publication number: 20160267992Abstract: A semiconductor memory device includes a first block including a first memory string that includes a first memory cell and a first select transistor, a second block including a second memory string that includes a second memory cell and a second select transistor, a source line that is connected to the first memory string and the second memory string, and a controller that applies a source line voltage to the source line and a first voltage to a gate of the second select transistor during a program operation in which data is written to the first memory cell, the first voltage being greater than ground voltage and less than or equal to the source line voltage.Type: ApplicationFiled: March 3, 2016Publication date: September 15, 2016Inventors: Hiroshi MAEJIMA, Yuya SUZUKI, Hidehiro SHIGA, Tomonori KUROSAWA
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Publication number: 20160005470Abstract: A memory device includes a plurality of memory blocks, and a row decoder including a plurality of decoders including a first decoder and a second decoder, the first decoder being configured to output a first block selection signal for selecting one of the memory blocks and a control signal for causing the second decoder to output a second block selection signal for selecting another one of the memory blocks.Type: ApplicationFiled: September 16, 2015Publication date: January 7, 2016Inventors: Koji HOSONO, Tomonori KUROSAWA