Semiconductor device having plural power source voltage generators, and voltage supplying method

- KIOXIA CORPORATION

In one embodiment, a semiconductor device includes a reference voltage supply circuit configured to supply a first reference voltage and a second reference voltage. The device further includes a power source voltage supply circuit including a first power source voltage generator supplied with the first reference voltage and configured to generate a first power source voltage, and a second power source voltage generator supplied with the second reference voltage and configured to generate a second power source voltage, the power source voltage supply circuit being configured to supply the first power source voltage and the second power source voltage to a power source voltage line. The device further includes a voltage control circuit connected to the power source voltage line, and configured to control a value of the first reference voltage and a value the second reference voltage.

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Description
CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2019-166239, filed on Sep. 12, 2019, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a semiconductor device and a voltage supplying method.

BACKGROUND

When plural power source voltage generators (VDD generators) in a semiconductor device are simultaneously trimmed, the trimming may be made inappropriate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating a configuration of a NAND chip of a first embodiment;

FIG. 2 is a circuit diagram illustrating a configuration of a part of the NAND chip of the first embodiment;

FIG. 3 is a circuit diagram illustrating a configuration of a reference voltage supply circuit of the first embodiment;

FIG. 4 is a circuit diagram illustrating a configuration of a part of a NAND chip of a comparative example of the first embodiment;

FIGS. 5A and 5B are graphs illustrating operations of the NAND chip of the comparative example illustrated in FIG. 4;

FIGS. 6A and 6B are graphs illustrating operations of the NAND chip of the first embodiment; and

FIGS. 7A and 7B are additional graphs illustrating operations of the NAND chip of the first embodiment.

 DETAILED DESCRIPTION OF THE INVENTION

In one embodiment, a semiconductor device includes a reference voltage supply circuit configured to supply a first reference voltage and a second reference voltage. The device further includes a power source voltage supply circuit including a first power source voltage generator supplied with the first reference voltage and configured to generate a first power source voltage, and a second power source voltage generator supplied with the second reference voltage and configured to generate a second power source voltage, the power source voltage supply circuit being configured to supply the first power source voltage and the second power source voltage to a power source voltage line. The device further includes a voltage control circuit connected to the power source voltage line, and configured to control a value of the first reference voltage and a value the second reference voltage.

Embodiments will now be explained with reference to the accompanying drawings. In FIGS. 1 to 7B, the same components are denoted by the same reference numerals, and redundant description will not be repeated.

First Embodiment

FIG. 1 is a circuit diagram illustrating a configuration of a NAND chip 1 of a first embodiment. FIG. 1 illustrates the NAND chip 1 as an example of a semiconductor device, and a tester 2 connected to the NAND chip 1. In the present embodiment, the tester 2 is used to perform trimming processing for the NAND chip 1.

The NAND chip 1 includes a plurality of input/output (I/O) pads 1a, RE and BRE (read enable) pads 1b and 1c, and an applied voltage pad 1d. The IO pads 1a are used for inputting commands from the tester 2 to the NAND chip 1, and outputting data from the NAND chip 1 to the tester 2. The RE pad 1b is used for supplying a RE signal from the tester 2 to the NAND chip 1. The BRE pad 1c is used for supplying a BRE signal from the tester 2 to the NAND chip 1. The applied voltage pad 1d is used for supplying an applied voltage Vapp from the tester 2 to the NAND chip 1.

The NAND chip 1 further includes a memory cell array 11 including a plurality of memory cells, a controller 12 that controls operations of the NAND chip 1, a reference voltage supply circuit 13, a power source voltage supply circuit 14, and a determination circuit 15. The power source voltage supply circuit 14 includes a plurality of VDD generators 14a to 14d. The NAND chip 1 further includes a power source voltage line L1, a reference voltage line L2, a reference voltage line L3, an applied voltage line L4, and a flag signal line L5.

The reference voltage supply circuit 13 supplies a reference voltage VrefIO as an example of a first reference voltage, and a reference voltage Vref as an example of a second reference voltage. The reference voltage VrefIO is supplied via the reference voltage line L2 to the VDD generator 14a that is arranged for the IO pads 1a. On the other hand, the reference voltage Vref is supplied via the reference voltage line L3 to the VDD generators 14b to 14d that are arranged for components other than the IO pads 1a. The VDD generator 14a for the IO pads 1a is an example of a first power source voltage generator, and the remaining VDD generators 14b to 14d are examples of a second power source voltage generator.

The power source voltage supply circuit 14 supplies a power source voltage VDD to the power source voltage line L1. In the present embodiment, the IO pads 1a, the RE pad 1b, and the BRE pad is are electrically connected to each other via the power source voltage line L1. The VDD generators 14a to 14d are electrically connected to each other via the power source voltage line L1. Further, the VDD generator 14a is electrically connected to the IO pads 1a, the RE pad 1b, and the BRE pad is via the power source voltage line L1. The VDD generator 14b is electrically connected to the controller 12 via the power source voltage line L1.

The VDD generator 14a is provided for the IO pads 1a, and generates the power source voltage VDD based on the reference voltage VrefIO, and supplies the generated voltage to the IO pads is (and also to the RE and BRE pads 1b and 1c). The power source voltage VDD from the VDD generator 14a is an example of a first power source voltage. The VDD generators 14b to 14d are provided for the components other than the IO pads 1a, generate the power source voltage VDD based on the reference voltage Vref, and supply the generated voltage to portions other than the IO pads 1a. The power source voltage VDD from the VDD generators 14b to 14d is an example of a second power source voltage. In the present embodiment, the power source voltage VDD from the VDD generator 14b is supplied to the controller 12, and the power source voltage VDD from the VDD generators 14c and 14d is supplied to arithmetic circuits in the NAND chip 1.

The determination circuit 15 compares the voltage on the power source voltage line L1 (power source voltage VDD) with the voltage on the applied voltage line L4 (applied voltage Vapp), and outputs a flag signal FLG indicating a result of the comparison to the flag signal line L5. For example, when the power source voltage VDD from the VDD generator 14a is supplied to the power source voltage line L1, the determination circuit 15 compares the power source voltage VDD from the VDD generator 14a with the applied voltage Vapp, and outputs the flag signal FLG indicating the comparison result. The applied voltage Vapp is an example of the voltage for comparison, and the flag signal FLG is an example a signal indicating the comparison result.

The controller 12 receives the flag signal FLG from the flag signal line L5, and controls the value of the reference voltage VrefIO and the value of the reference voltage Vref based on the flag signal FLG. In the present embodiment, trimming processing for the NAND chip 1 is performed by controlling the values of the reference voltages VrefIO and Vref. The tester 2 controls operations of the controller 12 in the trimming processing. The determination circuit 15 and the controller 12 are an example of a voltage control circuit.

Details of the controller 12, the reference voltage supply circuit 13, the power source voltage supply circuit 14, and the determination circuit 15, and details of the trimming processing will be described below with reference to FIG. 2.

FIG. 2 is a circuit diagram illustrating a configuration of a part of the NAND chip 1 of the first embodiment.

FIG. 2 illustrates the controller 12, the reference voltage supply circuit 13, the power source voltage supply circuit 14, and the determination circuit 15 of the present embodiment, similar to FIG. 1. FIG. 2 further illustrates the reference voltage line L2 that supplies the reference voltage VrefIO from the reference voltage supply circuit 13 to the VDD generator 14a, the reference voltage line L3 that supplies the reference voltage Vref from the reference voltage supply circuit 13 to the VDD generators 14b to 14d, the power source voltage line L1 that supplies the power source voltage VDD from the VDD generators 14a to 14d to the determination circuit 15, the applied voltage line L4 that supplies the applied voltage Vapp to the determination circuit 15, and the flag signal line L5 that transmits the flag signal FLG from the determination circuit 15 to the controller 12.

The reference voltage supply circuit 13 includes a comparator 13a, a MOS transistor 13b, a variable resistor 13c that is an example of a first variable resistor, a variable resistor 13d that is an example of a second variable resistor, and a fixed resistor 13e. The MOS transistor 13b, the variable resistor 13c, the variable resistor 13d, and the fixed resistor 13e are connected in series between an external voltage Vext and the ground voltage. FIG. 2 illustrates a node N1 between the MOS transistor 13b and the variable resistor 13c, a node N2 between the variable resistor 13c and the variable resistor 13d, and a node N3 between the variable resistor 13d and the fixed resistor 13e. The node N1 is an example of a first node, the node N2 is an example of a second node, and the node N3 is an example of a third node.

The comparator 13a has a first input terminal to which a constant voltage (e.g., 1.2 V) is supplied, a second input terminal connected to the node N3, and an output terminal that outputs a comparison result between an input voltage of the first input terminal and an input voltage of the second input terminal. The MOS transistor 13b is, for example, a pMOS, which has a gate terminal connected to the output terminal of the comparator 13a, a source terminal disposed on the external voltage Vext side, and a drain terminal disposed on the node N1 side.

The variable resistor 13c is provided for generating the reference voltage VrefIO at the node N1, and is arranged between the node N1 and the node N2. In the present embodiment, the value of the reference voltage VrefIO may be changed by changing the resistance value of the variable resistor 13c. The reference voltage supply circuit 13 of the present embodiment supplies the reference voltage VrefIO from the node N1 to the VDD generator 14a.

The variable resistor 13d is provided for generating the reference voltage Vref at the node N2, and is arranged between the node N2 and the node N3. In the present embodiment, the value of the reference voltage Vref may be changed by changing the resistance value of the variable resistor 13d. The reference voltage supply circuit 13 of the present embodiment supplies the reference voltage Vref from the node N2 to the VDD generators 14b to 14d.

The fixed resistor 13e is provided for giving an influence to the voltage of the node N3, and is arranged between the node N3 and the ground voltage. The voltage of the node N3 is supplied to the second input terminal of the comparator 13a.

Each of the VDD generators 14a to 14d is a unity gain buffer configured by an operational amplifier. Accordingly, the operational amplifier configuring each of the VDD generators 14a to 14d includes a first input terminal connected to the reference voltage supply circuit 13 to receive the reference voltage VrefIO or the reference voltage Vref, an output terminal connected to the determination circuit 15 to output the power source voltage VDD, and a second input terminal connected to this output terminal to configure a feedback circuit. The VDD generators 14a to 14d are arranged in parallel with each other between the reference voltage supply circuit 13 and the determination circuit 15. FIG. 2 illustrates 1.85 V, 1.84 V, 1.85 V, and 1.83 V as exemplary offset voltages of the operational amplifiers of the VDD generators 14a to 14d.

The determination circuit 15 includes a comparator 15a. The comparator 15a includes a first input terminal to which the voltage of the power source voltage line L1 is supplied, a second input terminal to which the applied voltage Vapp is supplied, and an output terminal that outputs the flag signal FLG indicating a comparison result between an input voltage of the first input terminal and an input voltage of the second input terminal. The flag signal FLG of the present embodiment becomes 0 (low) when the voltage of the power source voltage line L1 is lower than the applied voltage Vapp and becomes 1 (high) when the voltage of the power source voltage line L1 is equal to or greater than the applied voltage Vapp. In FIG. 2, the power source voltage VDD having been input from the power source voltage supply circuit 14 to the first input terminal of the determination circuit 15 is 1.85 V.

The controller 12 receives the flag signal FLG from the determination circuit 15 and controls, based on the flag signal FLG, the value of the reference voltage VrefIO and the value of the reference voltage Vref. Specifically, the controller 12 controls the value of the reference voltage VrefIO by outputting a control signal FIO<1:0> for controlling the resistance value of the variable resistor 13c and controls the value of the reference voltage Vref by outputting a control signal F<4:0> for controlling the resistance value of the variable resistor 13d.

When performing the trimming processing using the reference voltage Vref, the controller 12 operates in the following manner. When the flag signal FLG is low, the controller 12 counts up the value of the control signal F so that the resistance value of the variable resistor 13d increases with elapsing time. When the control signal F is transmitted to the variable resistor 13d, the resistance value of the variable resistor 13d increases with elapsing time. As a result, the value of the reference voltage Vref increases with elapsing time. Subsequently, when the flag signal FLG changes to high, the trimming processing using the reference voltage Vref terminates.

Similarly, when performing the trimming processing using the reference voltage VrefIO, the controller 12 operates in the following manner. When the flag signal FLG is low, the controller 12 counts up the value of the control signal FIO so that the resistance value of the variable resistor 13c increases with elapsing time. When the control signal FIO is transmitted to the variable resistor 13c, the resistance value of the variable resistor 13c increases with elapsing time. As a result, the value of the reference voltage VrefIO increases with elapsing time. Subsequently, when the flag signal FLG changes to high, the trimming processing using the reference voltage VrefIO terminates.

The trimming processing using the reference voltages Vref and VrefIO will be described in detail below.

FIG. 3 is a circuit diagram illustrating a configuration of the reference voltage supply circuit 13 of the first embodiment. For example, the variable resistor 13c, the variable resistor 13d, and the fixed resistor 13e of the present embodiment may be configured as illustrated in FIG. 3.

The variable resistor 13c includes four MOS transistors T10, T11, T12, and T13, and three resistors R11, R12, and R13. The MOS transistors T10, T11, T12, and T13 are arranged in parallel with each other between the node N1 and the node N2. The resistor R11 is arranged between the MOS transistors T10 and T11. The resistor R12 is arranged between the MOS transistors T11 and T12. The resistor R13 is arranged between the MOS transistors T12 and T13. FIG. 3 further illustrates a node NrefIO between the node N1 and the MOS transistor T13. The voltage of the node NrefIO is the reference voltage VrefIO and is the same as that of the node N1. The node N1 is electrically connected to the VDD generator 14a via the node NrefIO. The number of the MOS transistors in the variable resistor 13c may be other than four, and the number of the resistors in the variable resistor 13c may be other than three.

As illustrated in FIG. 3, the MOS transistors T10 to T13 and the resistors R11 to R13 in the variable resistor 13c configure a digital analog converter (DAC). Accordingly, when a digital signal is input to gate terminals of the MOS transistors T10 to T13, an analog signal converted from the digital signal is output from the variable resistor 13c.

The controller 12 (FIG. 2) of the present embodiment outputs the control signal FIO for controlling the resistance value of the variable resistor 13c. The control signal FIO is a digital signal indicating a digital value corresponding to the resistance value of the variable resistor 13c and is input to the gate terminals of the MOS transistors T10 to T13. As a result, the resistance value of the variable resistor 13c changes to the digital value indicated by the control signal FIO, and the reference voltage VrefIO changes correspondingly. The reference voltage VrefIO corresponds to the above-described analog signal. In this manner, the variable resistor 13c converts the digital value indicating the value of the control signal FIO into the analog value indicating the value of the reference voltage VrefIO.

The variable resistor 13d includes four MOS transistors T20, T21, T22, and T23 and four resistors R20, R21, R22, and R23. The MOS transistors T20, T21, T22, and T23 are arranged in parallel with each other between the node N2 and the node N3. The resistor R20 is arranged between the node N3 and the MOS transistor T20. The resistor R21 is arranged between the MOS transistors T20 and T21. The resistor R22 is arranged between the MOS transistors T21 and T22. The resistor R23 is arranged between the MOS transistors T22 and T23. FIG. 3 further illustrates a node Nref between the node N2 and the MOS transistor T23. The voltage of the node Nref is the reference voltage Vref and is the same as that of the node N2. The node N2 is electrically connected to the VDD generators 14b to 14d via the node Nref. The number of the MOS transistors in the variable resistor 13d may be other than four, and the number of the resistors in the variable resistor 13d may be other than four.

As illustrated in FIG. 3, the MOS transistors T20 to T23 and the resistors R21 to R23 in the variable resistor 13d configure a DAC. Accordingly, when a digital signal is input to gate terminals of the MOS transistors T20 to T23, an analog signal converted from the digital signal is output from the variable resistor 23d.

The controller 12 of the present embodiment outputs the control signal F for controlling the resistance value of the variable resistor 13d. The control signal F is a digital signal indicating a digital value corresponding to the resistance value of the variable resistor 13d and is input to the gate terminals of the MOS transistors T20 to T23. As a result, the resistance value of the variable resistor 13d changes to the digital value indicated by the control signal F, and the reference voltage Vref changes correspondingly. The reference voltage Vref corresponds to the above-described analog signal. In this manner, the variable resistor 13d converts the digital value indicating the value of the control signal F into the analog value indicating the value of the reference voltage Vref.

The fixed resistor 13e includes one resistor R30. The resistor R30 is arranged between the node N3 and the ground voltage. Two or more resistors may be provided in the fixed resistor 13e.

Next, the trimming processing using the reference voltages Vref and VrefIO will be described again with reference to FIG. 2.

The trimming processing of the present embodiment includes first trimming processing to be performed using the reference voltage Vref and second trimming processing to be subsequently performed using the reference voltage VrefIO. In the first trimming processing, all the VDD generators 14a to 14d are trimmed using the reference voltage Vref. In the second trimming processing, only the VDD generator 14a among the VDD generators 14a to 14d is trimmed using the reference voltage VrefIO.

In the first trimming processing, the resistance value of the variable resistor 13c is fixed to zero and the resistance value of the variable resistor 13d is caused to increase with elapsing time. Accordingly, the value of the reference voltage Vref increases with elapsing time. On the other hand, since the variable resistor 13c is zero, the value of the reference voltage VrefIO becomes equal to the value of the reference voltage Vref (VrefIO=Vref). Accordingly, the reference voltage Vref that increases with elapsing time is supplied to the VDD generators 14b to 14d. The reference voltage VrefIO, which is the same as the reference voltage Vref, is supplied to the VDD generator 14a. That is, in the first trimming processing, the same reference voltage Vref is supplied to all the VDD generators 14a to 14d.

In the first trimming processing, all the VDD generators 14a to 14d are operated to perform trimming to 1.85 V. Specifically, by counting up the value of the control signal F, the reference voltage Vref is caused to increase with elapsing time and the power source voltage VDD to be input to the determination circuit 15 is caused to increase so as to reach 1.85 V. On the other hand, the applied voltage Vapp is set to 1.85 V. Accordingly, when the power source voltage VDD reaches 1.85 V, the value of the flag signal FLG changes from 0 to 1. In the first trimming processing, the value of the control signal F at the time when the power source voltage VDD has reached 1.85 V is determined as a trim value. The trim value is stored inside or outside the NAND chip 1.

In the second trimming processing, the value of the control signal F is fixed to the above-described trim value and, while the resistance value of the variable resistor 13d is fixed, the resistance value of the variable resistor 13c is caused to increase with elapsing time. Accordingly, the reference voltage VrefIO becomes higher than the reference voltage Vref (VrefIO>Vref), and the value of the reference voltage VrefIO increases with elapsing time. In the second trimming processing, the reference voltage VrefIO higher than the reference voltage Vref is supplied to the VDD generator 14a.

In the second trimming processing, only the VDD generator 14a among the VDD generators 14a to 14d is operated to perform trimming to 1.85 V. Specifically, by counting up the value of the control signal FIO, the reference voltage VrefIO is caused to increase with elapsing time and the power source voltage VDD to be input to the determination circuit 15 is caused to increase so as to reach 1.85 V. On the other hand, the applied voltage Vapp is set to 1.85 V. Accordingly, when the power source voltage VDD reaches 1.85 V, the value of the flag signal FLG changes from 0 to 1. In the second trimming processing, the value of the control signal FIO at the time when the power source voltage VDD has reached 1.85 V is determined as the trim value. The trim value is stored inside or outside the NAND chip 1.

Next, a comparative example of the NAND chip 1 of the first embodiment will be described. Advantages of the trimming processing of the first embodiment will be described through comparison between the first embodiment and the comparative example.

FIG. 4 is a circuit diagram illustrating a configuration of a part of the comparative example of the NAND chip 1 of the first embodiment.

In the NAND chip 1 of this comparative example, the configuration illustrated in FIG. 2 is replaced by the configuration illustrated in FIG. 4. FIG. 4 illustrates a controller 12, a reference voltage supply circuit 13, a power source voltage supply circuit 14, and a determination circuit 15 of the comparative example.

The reference voltage supply circuit 13 of the comparative example does not include the variable resistor 13c. Accordingly, a node N2 of the reference voltage supply circuit 13 is electrically connected not only to VDD generators 14b to 14d but also to a VDD generator 14a. The reference voltage Vref is supplied to all the VDD generators 14a to 14d. FIG. 4 illustrates 1.83 V, 1.84 V, 1.85 V, and 1.83 V as exemplary offset voltages of the operational amplifiers of the VDD generators 14a to 14d. The trimming processing of the comparative example includes only the first trimming processing using the reference voltage Vref.

FIGS. 5A and 5B are graphs illustrating operations of the comparative example of the NAND chip 1 illustrated in FIG. 4.

Each of FIGS. 5A and 5B illustrates temporal changes of VDDIO that represents the power source voltage VDD supplied from the VDD generator 14a for the IO pads 1a, VDDX that represents the power source voltage VDD supplied from any one of the remaining VDD generators 14b to 14d, and ICCO that represents the consumption current of the NAND chip 1. FIG. 5A illustrates temporal changes in the case of VDDIO>VDDX and FIG. 5B illustrates temporal changes in the case of VDDIO<VDDX.

In the trimming processing (i.e., the first trimming processing) of the comparative example, all the VDD generators 14a to 14d are simultaneously trimmed in the state where the consumption current of the NAND chip 1 is zero. Therefore, when there is a difference in the value of the supplied power source voltage VDD among the VDD generators 14a to 14d, trimming suitable for the VDD generator supplying the highest power source voltage VDD is performed.

Accordingly, when the VDD generator 14a for the IO pads 1a supplies the highest power source voltage VDD, trimming suitable for the VDD generator 14a is performed (see FIG. 5A). On the other hand, when any one of the remaining VDD generators 14b to 14d supplies the highest power source voltage VDD, trimming that is not suitable for the VDD generator 14a may be performed (see FIG. 5B). FIG. 5B illustrates a state where the power source voltage VDD of the VDD generator 14a greatly drops as indicated by the symbol ΔV when the consumption current of the NAND chip 1 steeply increases.

It is considered that the speed of input/output signals at the IO pads 1a increases as the generation of the NAND chip 1 advances. Accordingly, inappropriately trimming the VDD generator 14a for the IO pads 1a is not desired. On the other hand, simultaneously trimming a plurality of VDD generators is desired to efficiently perform the trimming processing.

Therefore, the trimming processing of the present embodiment includes the first trimming processing for simultaneously trimming all the VDD generators 14a to 14d and the second trimming processing for trimming only the VDD generator 14a for the IO pads 1a. This makes it possible to efficiently perform the trimming processing while appropriately trimming the VDD generator 14a for the IO pads 1a.

FIGS. 6A and 6B are graphs illustrating operations of the NAND chip 1 of the first embodiment.

FIG. 6A illustrates the temporal change of each signal in the first trimming processing, more specifically, the control signal F input to the variable resistor 13d, the applied voltage Vapp input to the determination circuit 15, the power source voltage VDD input to the determination circuit 15, and the flag signal FLG output from the determination circuit 15.

In the first trimming processing, the power source voltage VDD increases with elapsing time by counting up the control signal F. When the power source voltage VDD reaches the applied voltage Vapp (e.g., 1.85 V), the flag signal FLG changes from 0 to 1. In the first trimming processing, the value of the control signal F at the time when the power source voltage VDD has reached the applied voltage Vapp is determined as the trim value.

FIG. 6B illustrates the temporal change of each signal in the second trimming processing, more specifically, the control signal FIO input to the variable resistor 13c, the applied voltage Vapp input to the determination circuit 15, the power source voltage VDD input to the determination circuit 15, and the flag signal FLG output from the determination circuit 15.

In the second trimming processing, the power source voltage VDD from the VDD generator 14a increases with elapsing time by counting up the control signal FIO while fixing the value of the control signal F to the trim value. When the power source voltage VDD reaches the applied voltage Vapp (e.g., 1.85 V), the flag signal FLG changes from 0 to 1. In the second trimming processing, the value of the control signal FIO at the time when the power source voltage VDD has reached the applied voltage Vapp is determined as the trim value.

FIGS. 7A and 7B are additional graphs illustrating operations of the NAND chip 1 of the first embodiment.

FIG. 7A illustrates distributions of the power source voltage VDD after the first trimming, and FIG. 7B illustrates distributions of the power source voltage VDD after the second trimming. Specifically, FIGS. 7A and 7B illustrate distributions of the power source voltage VDD supplied from the VDD generator 14a for the IO pads 1a and distributions of the power source voltage VDD supplied from the remaining VDD generators 14b to 14d.

FIG. 7A illustrates the distribution of the power source voltage VDD of the VDD generator 14a that does not reach 1.85 V, as an inappropriate trimming result for the VDD generator 14a. On the other hand, FIG. 7B illustrates the distribution of the power source voltage VDD of the VDD generator 14a that reaches 1.85 V, as an appropriate trimming result for the VDD generator 14a. Therefore, when the consumption current of the NAND chip 1 steeply increases, the power source voltage VDD of the VDD generator 14a can be suppressed from dropping.

FIG. 4 (comparative example) illustrates 1.83 V as an example of the offset voltage of the VDD generator 14a, FIG. 2 (first embodiment) illustrates 1.85 V as an example of the offset voltage of the VDD generator 14a. In the comparative example, the offset voltage becomes 1.83 V because of the first trimming processing. On the other hand, in the first embodiment, after the offset voltage has once become 1.83 V through the first trimming processing, the offset voltage becomes 1.85 V because of the second trimming processing. Therefore, the result illustrated in FIG. 7B can be obtained.

As described above, the NAND chip 1 of the present embodiment includes the reference voltage supply circuit 13 that supplies the power source voltage Vref to the VDD generators 14b to 14d and also supplies the power source voltage VrefIO to the VDD generator 14a. Therefore, according to the present embodiment, it is possible to efficiently trim all the VDD generators 14a to 14d while appropriately trimming the VDD generator 14a. Therefore, the plurality of VDD generators 14a to 14d can be appropriately trimmed.

In the present embodiment, the power source voltage supply circuit 14 includes four VDD generators 14a to 14d, but may include N VDD generators where N is an integer of two or more. In this case, the trimming processing may include first trimming processing for trimming all the N VDD generators and second trimming processing for trimming only one of the N VDD generators. In the second trimming processing, two or more of the N VDD generators may be trimmed.

Although the VDD generator 14a for the IO pads 1a is subjected to the second trimming processing of the present embodiment, a VDD generator for anything but the IO pads 1a may be subjected to the second trimming processing.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims

1. A semiconductor device comprising:

a reference voltage supply circuit configured to supply a first reference voltage and a second reference voltage;
a power source voltage supply circuit including a first power source voltage generator supplied with the first reference voltage and configured to generate a first power source voltage, and a second power source voltage generator supplied with the second reference voltage and configured to generate a second power source voltage, the power source voltage supply circuit being configured to supply the first power source voltage and the second power source voltage to a power source voltage line; and
a voltage control circuit connected to the power source voltage line, and configured to control a value of the first reference voltage and a value of the second reference voltage,
wherein:
the reference voltage supply circuit includes a first variable resistor configured to change the value of the first reference voltage, and a second variable resistor configured to change the value of the second reference voltage,
the first variable resistor is provided between a first node and a second node,
the second variable resistor is provided between the second node and a third node, and
the reference voltage supply circuit supplies the first reference voltage from the first node to the first power source voltage generator, and supplies the second reference voltage from the second node to the second power source voltage generator.

2. The device of claim 1, wherein each of the first variable resistor and the second variable resistor configures a digital analog converter including a plurality of transistors and a plurality of resistances.

3. The device of claim 1, wherein the first variable resistor and the second variable resistor are connected in series.

4. The device of claim 1, wherein the voltage control circuit controls the value of the first reference voltage by controlling a resistance value of the first variable resistor, and controls the value of the second reference voltage by controlling a resistance value of the second variable resistor.

5. The device of claim 1, wherein the voltage control circuit controls the value of the second reference voltage when trimming the first and second power source voltage generators, and controls the value of the first reference voltage when trimming only the first power source voltage generator of the first and second power source voltage generators.

6. The device of claim 1, wherein the voltage control circuit includes:

a determination circuit configured to compare a voltage on the power source voltage line with a voltage for comparison, and output a signal indicating a result of the comparison, and
a controller supplied with the signal from the determination circuit, and configured to control the value of the first reference voltage and the value of the second reference voltage.

7. The device of claim 1, wherein:

the first power source voltage is a power source voltage for an input/output pad of the semiconductor device, and
the second power source voltage is a power source voltage for a pad other than the input/output pad of the semiconductor device.

8. The device of claim 1, wherein each of the first and second power source voltage generators is a unity gain buffer.

9. A voltage supplying method comprising:

supplying a first reference voltage and a second reference voltage;
generating a first power source voltage from a first power source voltage generator to which the first reference voltage is supplied, generating a second power source voltage from a second power source voltage generator to which the second reference voltage is supplied, and supplying the first power source voltage and the second power source voltage to a power source voltage line; and
controlling a value of the first reference voltage and a value of the second reference voltage by a voltage control circuit connected to the power source voltage line,
wherein:
the method further comprises changing the value of the first reference voltage with a first variable resistor, and changing the value of the second reference voltage with a second variable resistor,
the first variable resistor is provided between a first node and a second node,
the second variable resistor is provided between the second node and a third node, and
the first reference voltage is supplied from the first node to the first power source voltage generator, and the second reference voltage is supplied from the second node to the second power source voltage generator.

10. The method of claim 9, wherein each of the first variable resistor and the second variable resistor configures a digital analog converter including a plurality of transistors and a plurality of resistances.

11. The method of claim 9, wherein the first variable resistor and the second variable resistor are connected in series.

12. The method of claim 9, wherein the voltage control circuit controls the value of the first reference voltage by controlling a resistance value of the first variable resistor, and controls the value of the second reference voltage by controlling a resistance value of the second variable resistor.

13. The method of claim 9, wherein the voltage control circuit controls the value of the second reference voltage when trimming the first and second power source voltage generators, and controls the value of the first reference voltage when trimming only the first power source voltage generator of the first and second power source voltage generators.

14. The method of claim 9, wherein the voltage control circuit includes:

a determination circuit configured to compare a voltage on the power source voltage line with a voltage for comparison, and output a signal indicating a result of the comparison, and
a controller supplied with the signal from the determination circuit, and configured to control the value of the first reference voltage and the value of the second reference voltage.

15. The method of claim 9, wherein:

the first power source voltage is a power source voltage for an input/output pad of the semiconductor device, and
the second power source voltage is a power source voltage for a pad other than the input/output pad of the semiconductor device.

16. The method of claim 9, wherein each of the first and second power source voltage generators is a unity gain buffer.

Referenced Cited
U.S. Patent Documents
5838145 November 17, 1998 Poon
5963439 October 5, 1999 Wuidart
6023133 February 8, 2000 Leung
6339344 January 15, 2002 Sakata
6424134 July 23, 2002 Morishita
6683442 January 27, 2004 Ferencz
7312652 December 25, 2007 Brox
7411183 August 12, 2008 Overney
7852248 December 14, 2010 Keramat
8531171 September 10, 2013 Sutardja
8816658 August 26, 2014 De Vita
9958889 May 1, 2018 Pons
10325667 June 18, 2019 Bushnaq et al.
20010006342 July 5, 2001 Kusumoto
20010011886 August 9, 2001 Kobayashi
20010028282 October 11, 2001 Nishibe
20030052661 March 20, 2003 Tachimori
20030080795 May 1, 2003 Okamoto
20040071191 April 15, 2004 Sim
20040185814 September 23, 2004 Inamori
20050099224 May 12, 2005 Itoh
20060158165 July 20, 2006 Inn
20070018623 January 25, 2007 Lopata
20070024363 February 1, 2007 Cho
20070285152 December 13, 2007 Fujita
20080136396 June 12, 2008 Heilmann
20080174290 July 24, 2008 Ogiwara
20090290428 November 26, 2009 Noh
20110215781 September 8, 2011 Sasaki
20110260783 October 27, 2011 Kawasaki
20110279101 November 17, 2011 Sasaki
20120062275 March 15, 2012 Hiraki
20120169305 July 5, 2012 Kwon
20120212201 August 23, 2012 Lee
20130113447 May 9, 2013 Kadanka
20130162227 June 27, 2013 Kodama
20130214869 August 22, 2013 Matsuzaki
20130271095 October 17, 2013 Jackum
20140003164 January 2, 2014 Fifield
20140167719 June 19, 2014 Chu
20140191742 July 10, 2014 Kung
20140266118 September 18, 2014 Chern
20140347130 November 27, 2014 Iijima
20150042306 February 12, 2015 Kim
20150130439 May 14, 2015 Wang
20160116926 April 28, 2016 Kim
20160276265 September 22, 2016 Iwabuchi
20160276287 September 22, 2016 Iwabuchi
20170241807 August 24, 2017 Hatakeyama
20170365336 December 21, 2017 Lin
20190155323 May 23, 2019 Kim
20210041509 February 11, 2021 Jiang
Foreign Patent Documents
2019053799 April 2019 JP
Patent History
Patent number: 11209846
Type: Grant
Filed: Jul 29, 2020
Date of Patent: Dec 28, 2021
Patent Publication Number: 20210080984
Assignee: KIOXIA CORPORATION (Tokyo)
Inventors: Kazuhiko Satou (Yokohama Kanagawa), Tomonori Kurosawa (Zama Kanagwa), Dai Nakamura (Fujisawa Kanagawa)
Primary Examiner: Thienvu V Tran
Assistant Examiner: Nusrat Quddus
Application Number: 16/941,801
Classifications
Current U.S. Class: Including Pre Or Post Regulation (323/266)
International Classification: G05F 1/46 (20060101); G05F 1/648 (20060101);