Patents by Inventor Tomoo Kimura

Tomoo Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9513720
    Abstract: A stylus detecting device detects a pointed position which is a position pointed to by a stylus, and includes a first camera; a second camera; and a control unit including an axis detecting unit that detects a three-dimensional position and attitude of an axis of the stylus by using two images captured respectively by the first and second cameras, and a pointed position detecting unit that calculates as the pointed position a point of intersection between a straight line indicated by the axis of the stylus whose three-dimensional position and attitude have been detected by the axis detecting unit and a target plane having a predetermined positional relationship with respect to the first and second cameras.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: December 6, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Shinsuke Ogata, Akihiro Miyazaki, Takeshi Shimamoto, Tomoo Kimura
  • Publication number: 20160034113
    Abstract: The display apparatus having a touch panel allows increased operability when performing a plurality of touch operations. The display apparatus having a touch panel includes: a display screen capable of displaying information in accordance with the touch operation, a first display region, a second display region, and a display controller. The first display region is displayed on the display screen, and displays the information in accordance with touch information acquired by an OS. The second display region is displayed on the display screen along with the first display region, and displays the information in accordance with the touch information acquired by a predetermined application without via the OS. The display controller performs a display such that the second display region does not overlap with the first display region on a periphery of the display screen.
    Type: Application
    Filed: July 28, 2015
    Publication date: February 4, 2016
    Inventors: Tomoo KIMURA, Kiyoshi NAKANISHI, Shinya KUSUHARA, Seiji KUBO, Takeshi SHIMAMOTO
  • Publication number: 20160034128
    Abstract: The display apparatus having a touch-panel includes: a display screen capable of displaying information in accordance with the touch-operation, a first display region, a second display region, and a display controller. The first display region is displayed on the display screen, and displays the information in accordance with touch-information acquired by an OS. The second display region is displayed on the display screen along with the first display region, and displays the information in accordance with the touch-information acquired by a predetermined application without via the OS. The display controller performs a display of the first display region and a display of the second display region, on the display screen in accordance with the touch-operation. The display controller moves the first display region in accordance with the touch-information acquired by the OS when the first display region on the display screen is moved by dragging over the second display region.
    Type: Application
    Filed: August 4, 2015
    Publication date: February 4, 2016
    Inventors: Tomoo KIMURA, Kiyoshi NAKANISHI, Shinya KUSUHARA
  • Publication number: 20150091831
    Abstract: The display device including a touch panel comprises a display unit having a screen that displays information according to a touch operation, and a controller that detects a plurality of contact positions on the screen according to the touch operation and controls the display unit to display first selection information at a position spaced from the plurality of contact positions by a predetermined distance. When at least one contact position of the plurality of contact positions is moved in the screen, the display unit moves and displays the first selection information on the screen to and at a position spaced from the moved contact position by the predetermined distance. The display device with a touch panel is easy for a user to operate by touching.
    Type: Application
    Filed: September 24, 2014
    Publication date: April 2, 2015
    Inventors: Kiyoshi NAKANISHI, Shunichi KUROMARU, Tomoo KIMURA, Hiromichi NISHIYAMA
  • Publication number: 20140285475
    Abstract: A stylus detecting device detects a pointed position which is a position pointed to by a stylus, and includes a first camera; a second camera; and a control unit including an axis detecting unit that detects a three-dimensional position and attitude of an axis of the stylus by using two images captured respectively by the first and second cameras, and a pointed position detecting unit that calculates as the pointed position a point of intersection between a straight line indicated by the axis of the stylus whose three-dimensional position and attitude have been detected by the axis detecting unit and a target plane having a predetermined positional relationship with respect to the first and second cameras.
    Type: Application
    Filed: August 21, 2013
    Publication date: September 25, 2014
    Inventors: Shinsuke Ogata, Akihiro Miyazaki, Takeshi Shimamoto, Tomoo Kimura
  • Patent number: 8818127
    Abstract: The picture quality of captured images can be improved with the degradation of clearness of image-captured object boundaries suppressed. An image processing apparatus (100) comprises: an image/distance acquiring unit (200) that acquires corresponding pixel pairs between left-eye and right-eye images, its depth information and its matching scores; a weight information calculating unit (300) that determines, for each of the pixel pairs, a weight of each of the pixels in a certain area including, as pixels of interest, the pixel pair on the basis of the depth information and the matching scores; and a pixel value superimposing unit (400) that applies, for each of the pixel pairs, the weight to the pixel values in the aforementioned certain area, thereby performing a smoothing process in at least one of the two images and that superimposes the two images using the values obtained by the smoothing process.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: August 26, 2014
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Keisuke Hayata, Hiroto Tomita, Tomoo Kimura
  • Publication number: 20140210748
    Abstract: An information processing apparatus 10a according to the present disclosure includes: a touchscreen panel 14 on which video is displayed and which accepts an operation that has been performed by a user; a detector 21 which detects the operation that has been performed by the user on the touchscreen panel 14; and a processor 20 which performs processing in response to the operation. If the user has performed the operation using a polyhedron input interface device 10b which has a plurality of sides in mutually different shapes, the detector 21 detects the shape of an area in which the input interface device 10b is in contact with the touchscreen panel to determine which side of the polyhedron has been used to perform the operation, and the processor 20 carries out processing that is associated with the side that has been used.
    Type: Application
    Filed: January 27, 2014
    Publication date: July 31, 2014
    Applicant: Panasonic Corporation
    Inventors: Atsushi NARITA, Kazunari FUJIWARA, Ryuji MIKI, Masami YOKOTA, Eric CHAN, Shigeru NATSUME, Silas WARREN, Simon ENEVER, Hao HUANG, Ryoichi YAGI, Kiyoshi NAKANISHI, Takeshi SHIMAMOTO, Seiji KUBO, Tomoo KIMURA, Hiromichi NISHIYAMA, Shogo MIKAMI
  • Patent number: 8780990
    Abstract: An imaging device includes a frame rate conversion unit synthesizing images captured at a second frame rate higher than a first frame rate to convert the images into a synthesized image having the first frame and a motion estimation unit performing motion estimation between consecutive frames of the images captured at the second frame. The imaging device also includes a motion vector synthesis unit synthesizing motion vectors having the second frame rate, to generate a synthesized motion vector of a target macroblock in the synthesized image, a motion blur amount determination unit counting, in an area surrounding the target macroblock, the number of macroblocks having the same synthesized motion vector as the target macroblock and comparing a value derived from the number of counted macroblocks with a threshold value, and a motion vector selection unit selecting the synthesized motion vector when the derived value determined to exceed the threshold value.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: July 15, 2014
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Ryuji Fuchikami, Kenji Shimizu, Tomoo Kimura
  • Patent number: 8493405
    Abstract: An image control device, which achieves energy saving effects without degradation of an image to be displayed, even if image data includes a fault, is configured to decode received image data into an image, generate display information based on the received image data, and output a decoded image and display information. The image control device receives image data, detects errors from the image data. For each error detected, the image control device specifies a fault image region containing an error from an entire image region of the image data, and inhibits use of the fault image region for generating display information that defines an image display condition according to which the display device performs the image display.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: July 23, 2013
    Assignee: Panasonic Corporation
    Inventors: Tomoo Kimura, Ryouta Hata
  • Publication number: 20130156339
    Abstract: The picture quality of captured images can be improved with the degradation of clearness of image-captured object boundaries suppressed. An image processing apparatus (100) comprises: an image/distance acquiring unit (200) that acquires corresponding pixel pairs between left-eye and right-eye images, its depth information and its matching scores; a weight information calculating unit (300) that determines, for each of the pixel pairs, a weight of each of the pixels in a certain area including, as pixels of interest, the pixel pair on the basis of the depth information and the matching scores; and a pixel value superimposing unit (400) that applies, for each of the pixel pairs, the weight to the pixel values in the aforementioned certain area, thereby performing a smoothing process in at least one of the two images and that superimposes the two images using the values obtained by the smoothing process.
    Type: Application
    Filed: March 23, 2012
    Publication date: June 20, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Keisuke Hayata, Hiroto Tomita, Tomoo Kimura
  • Patent number: 8144213
    Abstract: A frame brightness detecting unit 15 detects a frame brightness value of each of a plurality of image frames. A flicker spectrum detecting unit 16 detects, from the frame brightness values of 512 frames, spectrum values at frequencies, such as 100 Hz, 200 Hz, and 300 Hz. A brightness estimating unit 17 estimates a brightens value of a light source from the spectrum values. An encoding unit 18 uses a reciprocal of the estimated brightens value to determine a reference frame. The encoding unit 18 also uses the reciprocal in an evaluation function for motion vector estimation. The image frame is encoded using the motion vector.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: March 27, 2012
    Assignee: Panasonic Corporation
    Inventors: Ryuji Fuchikami, Ikuo Fuchigami, Tomoo Kimura
  • Publication number: 20110249750
    Abstract: An imaging device includes: a frame rate conversion unit synthesizing images captured at a second frame rate higher than a first frame rate to convert the images into a synthesized image having the first frame rate; a motion estimation unit performing a motion estimation between consecutive frames of the images captured at the second frame rate; a motion vector synthesis unit synthesizing motion vectors having the second frame rate obtained as a result of the motion estimation, so as to generate a synthesized motion vector of a target macroblock in the synthesized image; a motion blur amount determination unit which counts, in an area surrounding the target macroblock, the number of macroblocks having the same synthesized motion vector as that of the target macroblock and compares a value derived from the number of counted macroblocks with a threshold value, the counting and the comparison being performed for each target macroblock; and a motion vector selection unit selecting the synthesized motion vector wh
    Type: Application
    Filed: November 12, 2009
    Publication date: October 13, 2011
    Inventors: Ryuji Fuchikami, Kenji Shimizu, Tomoo Kimura
  • Publication number: 20100157093
    Abstract: A frame brightness detecting unit 15 detects a frame brightness value of each of a plurality of image frames. A flicker spectrum detecting unit 16 detects, from the frame brightness values of 512 frames, spectrum values at frequencies, such as 100 Hz, 200 Hz, and 300 Hz. A brightness estimating unit 17 estimates a brightens value of a light source from the spectrum values. An encoding unit 18 uses a reciprocal of the estimated brightens value to determine a reference frame. The encoding unit 18 also uses the reciprocal in an evaluation function for motion vector estimation. The image frame is encoded using the motion vector.
    Type: Application
    Filed: October 23, 2008
    Publication date: June 24, 2010
    Inventors: Ryuji Fuchikami, Ikuo Fuchigami, Tomoo Kimura
  • Publication number: 20100131791
    Abstract: A signal processing apparatus includes a signal processor a processing amount predictor for predicting a processing amount in the signal processor based on the signal data and outputting a processing amount prediction value, a processing amount observer for observing a processing amount of the signal processing executed by the signal processor and outputting a process completion value, and a control value decision section for deciding a voltage of the power and a frequency of the clock, which are supplied to the signal processor, based on the processing amount prediction value, the process completion value, and elapsed information indicating an elapsed time from a start of the signal processing. The power supplier supplies the power whose voltage is decided by the control value decision section to the signal processor, and the clock supplier supplies the clock whose frequency is decided by the control value decision section to the signal processor.
    Type: Application
    Filed: April 16, 2008
    Publication date: May 27, 2010
    Applicant: PANASONIC CORPORATION
    Inventor: Tomoo Kimura
  • Patent number: 7375580
    Abstract: A semiconductor integrated circuit having a circuit block including a MOS transistor that includes a bias input terminal, a source, and a substrate, in which the bias voltage is applied to the MOS transistor at a position of at least one of the source and the substrate through the bias input terminal, a setting unit operable to set up applying timing and releasing timing at which the bias voltage is applied to and released from the MOS transistor, and a bias voltage-applying unit operable to apply the bias voltage to the MOS transistor at the applying timing and the releasing timing. In the semiconductor integrated circuit, the setting unit sets up, as the releasing timing, timing prior to activation timing by a predetermined time period. An operation-requesting signal, to be sent out to the circuit block by the setting unit, is activated at the moment of the activation timing.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: May 20, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tomoo Kimura
  • Publication number: 20070273709
    Abstract: Provided is an image control device that achieves energy saving effects without degradation of an image to be displayed, even if image data includes a fault. The image control device is configured to decode the received image data into an image, generate display information based on the received image data, and output the decoded image and the display information. The image control device receives image data, detects errors from the image data. For each error detected, the image control device specifies a fault image region containing the error from an entire image region of the image data, and inhibits use of the fault image region for generating display information that defines an image display condition according to which the display device performs the image display.
    Type: Application
    Filed: May 21, 2007
    Publication date: November 29, 2007
    Inventors: Tomoo Kimura, Ryouta Hata
  • Patent number: 7146582
    Abstract: A dividing flip-flop FF2 is inserted in a cluster C of which the cluster length exceeds a predetermined cluster length. The flip-flop inserted cluster C is re-clustered, generating subdivided clusters C1 and C2. Therefore, the degree of freedom is increased in allocating clusters to a variable logic element such as an FPGA in a logical emulation device.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: December 5, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomoo Kimura, Kenichi Ishida, Tomoyuki Inomoto
  • Patent number: 7117462
    Abstract: In the circuit operation verifying method, initialization includes inputting circuit diagram data (a net list), specification information on respective circuit elements, and input data representing waveforms with time of voltages or currents used for operation simulation, and storing the circuit diagram data to memory. Operation of a semiconductor circuit to be verified is simulated using the circuit diagram data and the input data, and momentary voltage/current values at input terminals and the like of the circuit elements are stored in the memory. During the operation simulation, whether or not the circuit elements satisfy their voltage/current specifications and time specifications are concurrently verified based on the voltage/current values stored in the memory.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: October 3, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomoo Kimura, Tomonori Kataoka, Yoichi Nishida, Ikuo Fuchigami, Ken Kawai, Yasuhiro Ishiyama
  • Publication number: 20060176100
    Abstract: A semiconductor integrated circuit including: a circuit block including a MOS transistor that includes a bias input terminal, a source, and a substrate, in which the bias voltage is applied to the MOS transistor at a position of at least one of the source and the substrate through the bias input terminal; a setting unit operable to set up applying timing and releasing timing at which the bias voltage is applied to and released from the MOS transistor; and a bias voltage-applying unit operable to apply the bias voltage to the MOS transistor at the applying timing and the releasing timing. In the semiconductor integrated circuit, the setting unit sets up, as the releasing timing, timing prior to activation timing by a predetermined time period. An operation-requesting signal, to be sent out to the circuit block by the setting unit, is activated at the moment of the activation timing.
    Type: Application
    Filed: December 14, 2005
    Publication date: August 10, 2006
    Inventor: Tomoo Kimura
  • Publication number: 20050125642
    Abstract: A dynamically reconfigurable logic circuit device includes a plurality of dynamically reconfigurable processor units (DRPU) arranged in array, and a plurality of dynamically connecting units (DCU). The dynamically connecting units interconnect inputs and outputs of the dynamically reconfigurable processor units. Each of the dynamically reconfigurable processor units includes a plurality of arithmetic processing configurations, a plurality of input data storage units, and a plurality of output data storage units. The arithmetic processing configurations, input data storage units, and output data storage units are both selected and set up in accordance with an interrupting signal from an interrupt controller. Similarly, the interconnection of the dynamically reconfigurable processor units through the dynamically connecting units is performed in accordance with the interrupting signal.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 9, 2005
    Inventor: Tomoo Kimura