Abstract: A dividing flip-flop FF2 is inserted in a cluster C of which the cluster length exceeds a predetermined cluster length. The flip-flop inserted cluster C is re-clustered, generating subdivided clusters C1 and C2. Therefore, the degree of freedom is increased in allocating clusters to a variable logic element such as an FPGA in a logical emulation device.

Abstract: Each of terminals of a terminal group of a variable wiring element is connected to each three corresponding signal lines between three variable logic elements. The signal lines connected to the terminals of the terminal group of the variable wiring element can be used by any of the variable logic elements. Thus, depending on the number of signal lines used by each of the variable logic elements determined by the result of dividing of an under-verification circuit, the signal lines are selectively used. This allows efficient use of the signal lines.

Abstract: The output controlling circuit acquires temperature data of the variable logic elements that the temperature sensing units detect, and makes the output of the variable logic elements into high impedance where an excessive current flows into the variable logic elements and the temperature thereof excessively rises. Therefore, it is possible to prevent signals from being colliding with each other between variable logic elements, and between each of the variable logic elements and the external device, and it is possible to prevent an excessive current from continuously flowing into the variable logic elements and the external device.

Abstract: A current sense amplifier circuit is provided with a reference current generator for generating a reference current according to the characteristics of a memory cell, and a current comparator, and the current comparator compares the memory cell current with the reference current. Thereby, the range of the operating power supply voltage is increased. Further, a current sense amplifier circuit is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell that is set in multiple states.

Abstract: A current sense amplifier circuit is provided with a reference current generator for generating a reference current according to the characteristics of a memory cell, and a current comparator, and the current comparator compares the memory cell current with the reference current. Thereby, the range of the operating power supply voltage is increased. Further, a current sense amplifier circuit is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell that is set in multiple states.

Abstract: In a circuit operation verifying method, initialization includes inputting circuit diagram data (a net list), specification information on respective circuit elements, and in-put data representing waveforms with time of voltages or currents used for operation simulation, and expanding the circuit diagram data to a memory. Operation of a semiconductor circuit to be verified is simulated using the circuit diagram data and the input data, and momentary volt-age/current values at input terminals and the like of the circuit elements are stored in the memory. During the operation simulation, whether or not the circuit elements satisfy their voltage/current specifications and time specifications are concurrently verified based on the voltage/current values stored in the memory.

Abstract: A current sense amplifier circuit is provided with a reference current generator for generating a reference current according to the characteristics of a memory cell, and a current comparator, and the current comparator compares the memory cell current with the reference current. Thereby, the range of the operating power supply voltage is increased. Further, a current sense amplifier circuit is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell that is set in multiple states.

Abstract: A current sense amplifier circuit is provided with a reference current generator for generating a reference current according to the characteristics of a memory cell, and a current comparator, and the current comparator compares the memory cell current with the reference current. Thereby, the range of the operating power supply voltage is increased. Further, a current sense amplifier circuit is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell that is set in multiple states.

Abstract: The present invention provides a semiconductor memory which can reduce the area of a circuit for replacing defective memory cells with redundant memory cells as well as reduce the time for writing defect information.

Abstract: A semiconductor integrated circuit includes a booster for boosting a power supply voltage, and outputting the boosted voltage; an output circuit being supplied with the boosted voltage, and generating an output voltage from the boosted voltage; a reference voltage generator being supplied with the power supply voltage, and generating a reference voltage from the power supply voltage; a voltage divider being supplied with the output voltage from the output circuit, and dividing the output voltage with a predetermined voltage ratio; and a differential amplifier being supplied with the reference voltage and the divided voltage, and controlling the output circuit by supplying the output circuit with a voltage obtained by performing differential amplification on the reference voltage and the divided voltage according to the power supply voltage, thereby maintaining the output voltage from the output circuit at a predetermined voltage.

Abstract: There is provided a nonvolatile semiconductor memory which is capable of operating stably and performing high-speed access operation. A timing generation means 51 for generating timing signals which make a memory core unit 4 perform access operation uses first and second clocks of the same cycle and different phases. The timing generation means 51 generates timing signals for at least one first-half event among a plurality of read access events, according to the first clock, the phase of which precedes a phases of the second clock, and generates timing signals used for processing the remaining events, according to the second clock.

Abstract: A semiconductor memory device having nonvolatile memory cells arranged in matrix comprises and bit lines connected to drains of the memory cells. Latches provided for the respective bit lines or in the ratio of one latch to a number of bit lines, as are; transfer gates for electrically separating the respective latches from the bit lines. The device also having bit line voltage detection circuits for detecting voltages of the respective bit lines and latch reset circuits for inverting data stored in the respective latches in accordance with the outputs from the bit line voltage detection circuits. Therefore, data stored in each latch can be rewritten even by a very small memory cell current, resulting in stable program verify.