Patents by Inventor Tomoya Nishida

Tomoya Nishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device including a field effect transistor
    Patent number: 7579634
    Abstract: A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: August 25, 2009
    Assignee: Sony Corporation
    Inventors: Koji Onodera, Mitsuhiro Nakamura, Tomoya Nishida
  • Etching method, method of manufacturing semiconductor device, and semiconductor device
    Patent number: 7153710
    Abstract: In an etching method, an etching amount is controlled on the basis of the number of times an etching process is performed under the condition that an etching amount is determined independently of an etching time. Accordingly, the etching can be performed in step-by-step manner, whereby enabling the control of the etching amount at high precision.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: December 26, 2006
    Assignee: Sony Corporation
    Inventor: Tomoya Nishida
  • Semiconductor device and method of manufacturing semiconductor device
    Publication number: 20060157734
    Abstract: A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor.
    Type: Application
    Filed: January 12, 2006
    Publication date: July 20, 2006
    Inventors: Koji Onodera, Mitsuhiro Nakamura, Tomoya Nishida
  • Etching method, method of manufacturing semiconductor device, and semiconductor device
    Publication number: 20050118818
    Abstract: In an etching method, an etching amount is controlled on the basis of the number of times an etching process is performed under the condition that an etching amount is determined independently of an etching time. Accordingly, the etching can be performed in step-by-step manner, whereby enabling the control of the etching amount at high precision.
    Type: Application
    Filed: November 23, 2004
    Publication date: June 2, 2005
    Inventor: Tomoya Nishida