Abstract: An opening is formed through at least one dielectric material layer. A first metallic liner is formed on a bottom surface and sidewalls of the opening by depositing a first metallic material. A metal portion including an elemental metal or an intermetallic alloy of at least two elemental metals is formed on the first metallic liner. A second metallic liner including a second metallic material is formed directly on a top surface of the metal portion. The first metallic material and the second metallic material differ in composition. The first metallic liner and the second metallic liner contact an entirety of all surfaces of the metal portion. The first and second metallic liners can protect the metal portion from a subsequently deposited dielectric material layer, which may be formed as an air-gap dielectric layer after recessing the at least one dielectric material layer.

Abstract: A stack of layers is formed that includes first, second, and third dielectric layers. Contact plugs are then formed extending through the stack. Then a fourth dielectric layer is formed over the stack and contact plugs and trenches are formed through the fourth and third dielectric layers, extending to the second dielectric layer and exposing contact plugs.

Abstract: Isolation is provided by forming a first trench, depositing a cover layer on the bottom and sidewalls of the first trench, selectively removing the cover layer from the bottom and forming a second trench extending from the bottom of the first trench. The second trench is then substantially filled by thermal oxide formed by oxidation and the first trench is subsequently filled with a deposited dielectric.

Abstract: An initial etch forms a trench over first contact areas of a plurality of NAND strings, the initial etch also forming individual openings over second contact areas of the plurality of NAND strings. Material is added in the trench to reduce an area of exposed bottom surface of the trench while maintaining the individual openings without substantial reduction of bottom surface area. Subsequent further etching extends the trench and the plurality of individual openings.

Abstract: A NAND flash memory includes active areas separated by STI structures in a substrate with a layer of a first dielectric over the substrate. Portions of a second dielectric extend over the STI structures and another layer of the first dielectric extends over both the layer and portions, with contact holes extending through the dielectric layers at locations over the active areas in the semiconductor substrate.

Abstract: An initial etch forms a trench over first contact areas of a plurality of NAND strings, the initial etch also forming individual openings over second contact areas of the plurality of NAND strings. Material is added in the trench to reduce an area of exposed bottom surface of the trench while maintaining the individual openings without substantial reduction of bottom surface area. Subsequent further etching extends the trench and the plurality of individual openings.

Abstract: Contact holes are constrained to their designated active areas by etch-resistant walls so that they cannot contact adjacent active areas. Etch-resistant walls provide outer limits for any contact hole bending that may occur and thus keep contact holes substantially vertical. Mask openings for contact hole formation may be large so that they overlap etch-resistant walls.

Abstract: Trenches are formed partially through a sacrificial layer at locations where bit lines are to be formed with some sacrificial material overlying vias. The trenches are lined with a protective layer and then the trenches are extended to expose vias. Bit lines are formed. Then sacrificial material is removed from between bit lines while portions of the protective layer remain to protect the bit lines.

Abstract: A stack of layers is formed that includes first, second, and third dielectric layers. Contact plugs are then formed extending through the stack. Then a fourth dielectric layer is formed over the stack and contact plugs and trenches are formed through the fourth and third dielectric layers, extending to the second dielectric layer and exposing contact plugs.

Abstract: Isolation is provided by forming a first trench, depositing a cover layer on the bottom and sidewalls of the first trench, selectively removing the cover layer from the bottom and forming a second trench extending from the bottom of the first trench. The second trench is then substantially filled by thermal oxide formed by oxidation and the first trench is subsequently filled with a deposited dielectric.

Abstract: Contact holes are constrained to their designated active areas by etch-resistant walls so that they cannot contact adjacent active areas. Etch-resistant walls provide outer limits for any contact hole bending that may occur and thus keep contact holes substantially vertical. Mask openings for contact hole formation may be large so that they overlap etch-resistant walls.

Abstract: Air gaps are formed between conductive metal lines that have an inner barrier layer and an outer barrier layer. An etch step to remove sacrificial material is performed under a first set of process conditions producing a byproduct that suppresses further etching. A byproduct removal step performed under a second set of process conditions removes the byproduct.

Abstract: Air gaps are formed between conductive metal lines that have an inner barrier layer and an outer barrier layer. An etch step to remove sacrificial material is performed under a first set of process conditions producing a byproduct that suppresses further etching. A byproduct removal step performed under a second set of process conditions removes the byproduct.

Abstract: A semiconductor device comprises a first transistor including a first diffusion region, a first body region, and a second diffusion region, formed to align in a direction orthogonal to a main surface; a second transistor including a third diffusion region, a second body region, and a fourth diffusion region, formed to align in a direction orthogonal to the main surface; a first variable resistance element provided in the second diffusion region of the first transistor; a second variable resistance element provided in the fourth diffusion region of the second transistor; a bit line commonly connected to the first variable resistance element and the second variable resistance element; a first word line arranged on a first side of the first body region; a second word line arrange between a second side of the first body region and a first side of the second body region; and a third word line arranged on a second side of the second body region.

Abstract: A method of manufacturing a semiconductor device comprises: forming a processing target; forming a first supporter on the processing target; forming a first mask so as to contact one side surface of the first mask with a side surface of the first supporter; patterning the processing target using, as masks, the first mask and the first supporter; forming a second supporter so as to be contacted with a side surface of the processing target exposed in first processing step and the other side surface of the first mask; removing the first supporter; and patterning the processing target using, as masks, the first mask and the second supporter.

Abstract: A semiconductor device may include, but is not limited to: a first insulating film; a second insulating film over the first insulating film; a first memory structure between the first and second insulating films; and a third insulating film between the first and second insulating films. The first memory structure may include, but is not limited to: a heater electrode; and a phase-change memory element between the heater electrode and the second insulating film. The phase-change memory element contacts the heater electrode. The third insulating film covers at least a side surface of the phase-change memory element. Empty space is positioned adjacent to at least one of the heater electrode and the third insulating film.

Abstract: A method of manufacturing a semiconductor device comprises: forming a processing target; forming a first supporter on the processing target; forming a first mask so as to contact one side surface of the first mask with a side surface of the first supporter; patterning the processing target using, as masks, the first mask and the first supporter; forming a second supporter so as to be contacted with a side surface of the processing target exposed in first processing step and the other side surface of the first mask; removing the first supporter; and patterning the processing target using, as masks, the first mask and the second supporter.

Abstract: A method for manufacturing a semiconductor device includes: forming a first insulating film that covers a substrate; forming a conductive plug that penetrates the first insulating film; forming a hole portion on the conductive plug by partly removing upper part of the conductive plug, wherein the hole portion has a top surface of the conductive plug as a bottom surface, and has the first insulating film of a portion that covered the partly removed conductive plug as a sidewall; forming a sidewall insulating film that exposes a part of the bottom surface of the hole portion while covering the sidewall of the hole portion and a bottom portion of the hole portion; forming a variable resistance film that covers the sidewall insulating film and the bottom surface of the hole portion; and forming a conductive film that covers the variable resistance film.

Abstract: A semiconductor device may include, but is not limited to: a first insulating film; a second insulating film over the first insulating film; a first memory structure between the first and second insulating films; and a third insulating film between the first and second insulating films. The first memory structure may include, but is not limited to: a heater electrode; and a phase-change memory element between the heater electrode and the second insulating film. The phase-change memory element contacts the heater electrode. The third insulating film covers at least a side surface of the phase-change memory element. Empty space is positioned adjacent to at least one of the heater electrode and the third insulating film.

Abstract: A phase-change nonvolatile memory (PRAM) is constituted of a semiconductor substrate, a lower electrode, a first interlayer insulating film having a first hole, an impurity diffusion layer embedded in the first hole, a second interlayer insulating film having a second hole whose diameter is smaller than the diameter of the first hole, a phase-change recording layer, and an upper electrode. The impurity diffusion layer is constituted of two semiconductor layers having different conductivity types, wherein one semiconductor layer is constituted of a base portion and a projecting portion having a heating spot in contact with the phase-change recording layer, while the other semiconductor layer is formed to surround the projecting portion. A depletion layer is formed in proximity to the junction surface so as to reduce the diameter of the heating spot, thus reducing the current value Ireset for writing data in to the phase-change recording layer.