Patents by Inventor Tomoyuki Miyoshi

Tomoyuki Miyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110140199
    Abstract: A high voltage ESD protective diode having high avalanche withstand capability and capable of being formed by using manufacturing steps identical with those for a high voltage transistor to be protected, the device having a structure in which a gate oxide film is formed over a substrate surface at a PN junction formed of an N type low concentration semiconductor substrate constituting a cathode region and a P type low concentration diffusion region constituting an anode region, and a gate electrode which is disposed overriding the gate oxide film and a field oxide film is connected electrically by way of a gate plug with an anode electrode, whereby an electric field at the PN junction is moderated upon avalanche breakdown to obtain a high avalanche withstand capability. Further, the withstand voltage can be adjusted by changing the length of the field oxide film.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 16, 2011
    Inventors: Tomoyuki MIYOSHI, Shinichiro Wada, Yohei Yanagida
  • Publication number: 20110024838
    Abstract: There is provided a high withstand voltage LDMOS which is a MOS transistor formed on a semiconductor substrate and isolated by a trench, and a source region of which is sandwiched by a drain region, in which the metal layer gate wire connected to the gate electrode is led out outside the trench so as to pass over a P-type drift layer.
    Type: Application
    Filed: July 12, 2010
    Publication date: February 3, 2011
    Inventors: Keigo KITAZAWA, Junji Noguchi, Takayuki Oshima, Shinichiro Wada, Tomoyuki Miyoshi, Atsushi Itoh
  • Publication number: 20100078676
    Abstract: The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply.
    Type: Application
    Filed: July 20, 2009
    Publication date: April 1, 2010
    Inventors: Tomoyuki MIYOSHI, Shinichiro WADA, Yohei YANAGIDA