Patents by Inventor Tomoyuki Shibata

Tomoyuki Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10214198
    Abstract: A vehicle includes an engine, an MG (motor generator) 1, an MG2, a planetary gear device mechanically coupled to the engine and MG1 and MG2, a battery, a converter configured to boost a voltage from the battery, an inverter configured to perform a power conversion between the converter and MG1 or between the converter and MG2, and a controller. MG1 generates a counter-electromotive voltage when rotated by the engine, and a braking torque is generated as the counter-electromotive voltage becomes greater than the output voltage of the converter. During an inverter-less running control where the inverter is put into a gate shut-off state and the engine is driven to cause MG1 to generate the counter-electromotive torque, the controller decreases a voltage difference between the counter-electromotive voltage and the output voltage of the converter when a chargeable power of the battery is lower than a predetermined value.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: February 26, 2019
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tomoyuki Shibata, Takeshi Kishimoto, Masaya Amano, Takashi Ando, Yu Shimizu
  • Patent number: 10163469
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Publication number: 20180342071
    Abstract: According to an embodiment, a moving object tracking apparatus includes an acquiring unit, an associating unit, and an output control unit. The acquiring unit is configured to acquire a plurality of pieces of moving object information representing a moving object included in a photographed image. The associating unit is configured to execute an associating process for associating a plurality of pieces of the moving object information similar to each other as the moving object information of the same moving object for three or more pieces of the moving object information. The output control unit is configured to output the associated moving object information.
    Type: Application
    Filed: February 15, 2018
    Publication date: November 29, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoyuki SHIBATA, Yuto Yamaji
  • Publication number: 20180276471
    Abstract: According to one embodiment, an information processing device includes a processor and a memory. The processor determines whether an object included in an image belongs to a first group or not. The processor calculates at least one of first statistical information of an object determined to belong to the first group or second statistical information of an object determined not to belong to the first group. The processor stores at least one of the first statistical or the second statistical information in the memory. The processor executes display processing for at least one of the first statistical information or the second statistical information stored in the memory.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 27, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoyuki SHIBATA, Yuto YAMAJI, Hideo UMEKI
  • Publication number: 20180197018
    Abstract: According to an embodiment, an information processing device includes a memory and processing circuitry. The processing circuitry is configured to acquire a captured image; detect a plurality of targets included in the captured image; calculate target information representing at least one of a state or an attribute and reliability of the target information for each of the plurality of detected targets on the basic of the captured image; and estimate a distribution of the target information of the plurality of targets on the basis of a distribution of the target information of targets for which the reliability is higher than a set value.
    Type: Application
    Filed: August 1, 2017
    Publication date: July 12, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiaki NAKASU, Tomoyuki SHIBATA, Kazushige OUCHI
  • Publication number: 20180151207
    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.
    Type: Application
    Filed: November 30, 2016
    Publication date: May 31, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
  • Publication number: 20180144481
    Abstract: According to an embodiment, a moving object tracking device includes a memory having computer executable components stored therein; and a processor communicatively coupled to the memory. The processor is configured to perform acquiring a plurality of images; generating a plurality of pieces of tracking information indicating information obtained by tracking a moving object included in the images; generating first associated tracking information obtained by first association targeting the plurality of pieces of tracking information having a mutual time difference equal to or smaller than a threshold; generating second associated tracking information obtained by second association targeting the first associated tracking information and the tracking information, not associated by the first association, based on authentication information for identifying the moving object; and outputting the second associated tracking information.
    Type: Application
    Filed: August 3, 2017
    Publication date: May 24, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoyuki SHIBATA, Yuto YAMAJI
  • Publication number: 20180144074
    Abstract: According to an embodiment, a retrieving apparatus includes a memory having computer executable components stored therein; and a processor communicatively coupled to the memory. The processor is configured to obtain a first query including a relative expression; determine an evaluation method for retrieval targets according to the first query; and evaluate the retrieval targets with the determined evaluation method.
    Type: Application
    Filed: August 22, 2017
    Publication date: May 24, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuto YAMAJI, Tomoyuki Shibata
  • Publication number: 20180096734
    Abstract: Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that interfaces with a plurality of dice through a plurality of memory channels, each of the dice comprising a plurality of memory cells, and the interface chip comprising a test circuit. The test circuit includes: first and second terminals corresponding to the first and second memory channels respectively; a test terminal and a built in self test (BIST) circuit common to the first and second memory channels; and a selector coupled to the first and second terminals, the test terminal and the BIST circuit, and couples a first selected one of the first terminal, the test terminal and the BIST circuit to the first channel and a second selected one of the second terminal, the test terminal and the BIST circuit to the second channel.
    Type: Application
    Filed: December 6, 2017
    Publication date: April 5, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Ryota Suzuki
  • Patent number: 9934832
    Abstract: Apparatuses for monitoring a signal on a conductive via are described. An example apparatus includes: a controller, a first conductive via, a second conductive via and an evaluation circuit. The controller provides a clock signal as a first signal. The first conductive via provides a second signal responsive to the first signal. The second conductive via provides a third signal responsive to the second signal. Responsive to the third signal, the evaluation circuit provides an evaluation result signal. The evaluation result signal is indicative of a frequency of the clock signal, based on a delay of the third signal relative to the clock signal. The first conductive via, the second conductive via and the evaluation circuit may be included in an interface die. The evaluation circuit may detect whether a frequency of the first signal is below a first threshold frequency and may further provide the evaluation result signal.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: April 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Tomoyuki Shibata, Minehiko Uehara
  • Publication number: 20180082129
    Abstract: According to an embodiment, an information processing apparatus includes a memory and processing circuitry. The processing circuitry configured to acquire a captured image of an object on a first plane. The processing circuitry configured to detect a position and a size of the object in the captured image. The processing circuitry configured to determine, based on the position and the size of the object in the captured image, a mapping relation representing a relation between the position of the object in the captured image and a position of the object in a virtual plane that is the first plane when viewed from a predetermined direction. The processing circuitry configured to convert the position of the object in the captured image into the position of the object on the virtual plane, based on the mapping relation.
    Type: Application
    Filed: February 28, 2017
    Publication date: March 22, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuto YAMAJI, Tomoyuki SHIBATA, Tomoki WATANABE
  • Publication number: 20180075423
    Abstract: An information processing device according to an embodiment includes a determination unit and an output control unit. The determination unit is configured to determine an output position of output information about a state of a line, in real space, on the basis of structural information representing a structure of the line formed by objects included in an object image. The output control unit is configured to control output of the output information to the output position.
    Type: Application
    Filed: February 28, 2017
    Publication date: March 15, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Osamu YAMAGUCHI, Tomoyuki SHIBATA
  • Publication number: 20180039860
    Abstract: An image processing method according to an embodiment includes an image acquisition unit, a calculation unit, a region acquisition unit and an estimation unit. The image acquisition unit acquires a target image. The calculation unit calculates a density distribution of targets included in the target image. The estimation unit estimates the density distribution in a first region in the target image based on the density distribution in a surrounding region of the first region in the target image.
    Type: Application
    Filed: February 27, 2017
    Publication date: February 8, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiaki NAKASU, Quoc Viet PHAM, Masayuki MARUYAMA, Tomoyuki SHIBATA, Osamu YAMAGUCHI
  • Patent number: 9881693
    Abstract: Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that interfaces with a plurality of dice through a plurality of memory channels, each of the dice comprising a plurality of memory cells, and the interface chip comprising a test circuit. The test circuit includes: first and second terminals corresponding to the first and second memory channels respectively; a test terminal and a built in self test (BIST) circuit common to the first and second memory channels; and a selector coupled to the first and second terminals, the test terminal and the BIST circuit, and couples a first selected one of the first terminal, the test terminal and the BIST circuit to the first channel and a second selected one of the second terminal, the test terminal and the BIST circuit to the second channel.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Ryota Suzuki
  • Publication number: 20180005069
    Abstract: According to an embodiment, an information processing apparatus includes a memory and processing circuitry. The processing circuitry configured to acquire a plurality of input images captured at a specific place. The processing circuitry configured to adapt an estimation model used for detecting a target object included in images to the specific place based on the plurality of input images. The processing circuitry configured to output a result of determination of an adaptation state for the specific place in the estimation model.
    Type: Application
    Filed: February 22, 2017
    Publication date: January 4, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoyuki SHIBATA, Osamu YAMAGUCHI, Yuto YAMAJI, Masayuki MARUYAMA
  • Publication number: 20170365356
    Abstract: Apparatuses and methods of sharing error correction memory on an interface chip are described. An example apparatus includes: at least one memory chip having a plurality of first memory cells and an interface chip coupled to the at least one memory chip and having a control circuit and a storage area. The control circuit detects one or more defective memory cells of the first memory cells of the at least one memory chip. The control circuit further stores first defective address information of the one or more defective memory cells of the first memory cells into the storage area. The interface chip responds to the first defective address information and an access request to access the storage area in place of the at least one memory chip when the access request has been provided with respect to the one or more defective memory cells of the first memory cells.
    Type: Application
    Filed: June 15, 2016
    Publication date: December 21, 2017
    Applicant: Micron Technology, Inc.
    Inventors: Tomoyuki Shibata, Chikara Kondo, Hiroyuki Tanaka
  • Publication number: 20170344858
    Abstract: A control device includes one or more processors. The processors detect a target captured in an image, and calculate likelihood indicating whether the target is concealed. The processors decide on an output method for outputting the target according to the likelihood. The processors generate a display image based on the image and the decided output method.
    Type: Application
    Filed: February 23, 2017
    Publication date: November 30, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hidetaka OHIRA, Yuto YAMAJI, Tomoyuki SHIBATA, Osamu YAMAGUCHI
  • Publication number: 20170309319
    Abstract: Apparatuses for monitoring a signal on a conductive via are described. An example apparatus includes: a controller, a first conductive via, a second conductive via and an evaluation circuit. The controller provides a clock signal as a first signal. The first conductive via provides a second signal responsive to the first signal. The second conductive via provides a third signal responsive to the second signal. Responsive to the third signal, the evaluation circuit provides an evaluation result signal. The evaluation result signal is indicative of a frequency of the clock signal, based on a delay of the third signal relative to the clock signal. The first conductive via, the second conductive via and the evaluation circuit may be included in an interface die. The evaluation circuit may detect whether a frequency of the first signal is below a first threshold frequency and may further provide the evaluation result signal.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 26, 2017
    Applicant: Micron Technology, Inc.
    Inventors: Tomoyuki Shibata, Minehiko Uehara
  • Publication number: 20170270351
    Abstract: According to an embodiment, a calculation device includes a registerer, a first calculator, a receiver, and a second calculator. The registerer registers a plurality of patterns. The first calculator calculates a degree of closeness between the registered patterns. The receiver receives an input pattern. The second calculator calculates a first similarity value between the input pattern and a first registered pattern among the plurality of registered patterns, calculates second similarity values between the input pattern and one or more second registered patterns having a neighbor relationship with the first registered pattern among the plurality of registered patterns, and calculates a combined similarity value in which the first similarity value and the one or more second similarity values are combined.
    Type: Application
    Filed: September 7, 2016
    Publication date: September 21, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tomoyuki SHIBATA
  • Publication number: 20170256044
    Abstract: Disclosed is a device selecting apparatus including: processing circuitry. The processing circuitry is configured to: acquire an image including a plurality of devices provided in a real world; set one device in operation, set an image setting region corresponding to the one device on the image, and calculate an image congestion degree of persons existing in the image setting region; calculate a real setting region on the real world corresponding to the image setting region from a positional relationship between the image and the real world, and calculate a real congestion degree in the real setting region from the image congestion degree; and, when the real congestion degree meets a predetermined first criterion, select a stopped device other than the set device in operation based on a predetermined first selection rule, and output operation information of the selected stopped device.
    Type: Application
    Filed: September 8, 2016
    Publication date: September 7, 2017
    Inventors: Masayuki MARUYAMA, Osamu YAMAGUCHI, Tomoyuki SHIBATA