Abstract: This transmitter is provided with: a digital delay circuit which delays a 1-bit digital RF signal on the basis of another 1-bit digital RF signal; an amplifier which amplifies a signal output by the digital delay circuit; and a band-pass filter which allows signals in a prescribed frequency band, from among signals output by the amplifier, to pass. A signal output by the band-pass filter is input into a corresponding one antenna element from among a plurality of antenna elements, and controls the directionality of a beam formed by the plurality of antenna elements.

Abstract: This transmitter is provided with: a digital delay circuit which delays a 1-bit digital RF signal on the basis of another 1-bit digital RF signal; an amplifier which amplifies a signal output by the digital delay circuit; and a band-pass filter which allows signals in a prescribed frequency band, from among signals output by the amplifier, to pass. A signal output by the band-pass filter is input into a corresponding one antenna element from among a plurality of antenna elements, and controls the directionality of a beam formed by the plurality of antenna elements.

Abstract: The purpose of the present invention is to provide an amplifier having high signal-to-noise ratio of a transmitted signal and high electrical efficiency. Another purpose is to suppress complexity of amplifier's wiring connecting a signal generator that generates a binary digital signal and an amplification unit that amplifies the same. This amplifier generates a binary digital signal. The amplifier further generates a K-value digital signal (K is an integer greater than or equal to 3) from the binary digital signal and generating a plurality of binary digital signals from the K-value digital signal. The amplifier amplifies each of the plurality of binary digital signals, and combines the plurality of amplified binary digital signals and generating a combined signal having a substantially proportional relationship with the K-value digital signal.

Abstract: This ?? modulator is a ?? modulator using multiple integrators. The integrator: includes a plurality of stages of adder sequences, each of the adder sequences including a plurality of adders connected in series; performs feedback of a result of a second adder sequence as an input to a first adder sequence, the first adder sequence being a first stage of the plurality of stages, and the second adder sequence being a last stage of the plurality of stages; and processes inputs supplied to the plurality of adders of the first adder sequence and supplies it to the second adder sequence.

Abstract: In a digital transmitter, a digital RF signal generation unit executes digital modulation on I and Q signals to convert the I and Q signal into first and second digital RF signals, respectively, with a bit rate which is twice a carrier frequency. A retiming unit delays the first digital RF signal according to a clock signal with a frequency which is 4n times (n is an integer) the carrier frequency to output the delayed first digital RF signal and delays the phase of the second digital RF signal by 90 degrees with respect to an output of the first digital RF signal to output the delayed second digital RF signal. First and second amplifiers amplify the first and second digital RF signals output by the retiming unit, respectively. A combiner combines the amplified first and second digital RF signals to generate one signal sequence.

Abstract: Provided are a wireless access system provided with a remote unit capable of handling a high-frequency region without being made complicated, and a control method for the same. A wireless access system according to the present invention is provided with: a center unit (1); and a remote unit (3) that converts a baseband signal generated by the center unit (1) into a high-frequency signal and emits the high-frequency signal from an antenna (12). The center unit (1) includes a 1-bit modulator (5) that converts the baseband signal into a 1-bit signal on the basis of a generated clock signal and outputs the 1-bit signal.

Abstract: The purpose of the present invention is to provide an amplifier having high signal-to-noise ratio of a transmitted signal and high electrical efficiency. Another purpose is to suppress complexity of amplifier's wiring connecting a signal generator that generates a binary digital signal and an amplification unit that amplifies the same. This amplifier generates a binary digital signal. The amplifier further generates a K-value digital signal (K is an integer greater than or equal to 3) from the binary digital signal and generating a plurality of binary digital signals from the K-value digital signal. The amplifier amplifies each of the plurality of binary digital signals, and combines the plurality of amplified binary digital signals and generating a combined signal having a substantially proportional relationship with the K-value digital signal.

Abstract: In a digital transmitter, a digital RF signal generation unit executes digital modulation on I and Q signals to convert the I and Q signal into first and second digital RF signals , respectively, with a bit rate which is twice a carrier frequency. A retiming unit delays the first digital RF signal according to a clock signal with a frequency which is 4n times (n is an integer) the carrier frequency to output the delayed first digital RF signal and delays the phase of the second digital RF signal by 90 degrees with respect to an output of the first digital RF signal to output the delayed second digital RF signal. First and second amplifiers amplify the first and second digital RF signals output by the retiming unit, respectively. A combiner combines the amplified first and second digital RF signals to generate one signal sequence.

Abstract: This ?? modulator is a ?? modulator using multiple integrators. The integrator: includes a plurality of stages of adder sequences, each of the adder sequences including a plurality of adders connected in series; performs feedback of a result of a second adder sequence as an input to a first adder sequence, the first adder sequence being a first stage of the plurality of stages, and the second adder sequence being a last stage of the plurality of stages; and processes inputs supplied to the plurality of adders of the first adder sequence and supplies it to the second adder sequence.

Abstract: Provided are a wireless access system provided with a remote unit capable of handling a high-frequency region without being made complicated, and a control method for the same. A wireless access system according to the present invention is provided with: a center unit (1); and a remote unit (3) that converts a baseband signal generated by the center unit (1) into a high-frequency signal and emits the high-frequency signal from an antenna (12). The center unit (1) includes a 1-bit modulator (5) that converts the baseband signal into a 1-bit signal on the basis of a generated clock signal and outputs the 1-bit signal.

Abstract: An optical modulation unit outputs an optical signal generated by binary-modulating an input light. Phase modulation areas are formed on an optical wave guide. A drive circuit includes a plurality of drivers outputting drive signals according to an input digital signal to the phase modulation areas. A determination circuit determines the driver to be activated among the plurality of the drivers based on information expressing a transmission rate. A driver control circuit activates the driver specified by a result of a determination of the determination circuit and cuts off power supply to the driver other than the activated driver. A switching circuit switches connections between the plurality of the drivers and the phase modulation areas. A switching control circuit that controls the switching circuit to cause the drive signals to be applied from the activated driver to the phase modulation areas.

Abstract: The present invention includes optical phase modulation circuits (26A, 26B) as one and another transmission processing devices that transmit a plurality of pieces of data in a phase-synchronous manner, and one and another synchronization drive means (33A, 33B) for synchronously control transmission operations of the optical phase modulation circuits.

Abstract: To adequately perform sampling, a receiving device that solves problems that involve an increase in circuit area and an increase in cost, is provided. A/D converter 2 samples a coherent signal that is an analog signal in synchronization with a sampling clock signal so as to convert the analog signal into a digital signal. DSP 3 demodulates the digital signal converted by A/D converter 2 and computes a phase of the sampling clock signal in which an error rate of the digital signal is the minimum based on the demodulated digital signal. Sampling clock extraction circuit 4 extracts a clock signal having a symbol rate of the coherent signal therefrom. Phase adjustment circuit 5 adjusts the phase of the clock signal extracted by sampling clock extraction circuit 4 to the phase computed by DSP 3 and generates a clock signal having the adjusted phase as the sampling clock signal.

Abstract: An A/D conversion unit performs an A/D conversion operation twice during a hold period of an analog value. In a first conversion operation, the A/D conversion unit compares the analog value with a first reference voltage and outputs a comparison result as first converted data. In a second conversion operation, the A/D conversion unit compares the analog value with a second reference voltage and outputs a comparison result as second converted data. The second reference voltage is a voltage obtained by adding or subtracting a minimum resolution voltage to or from the first reference voltage. A digital processing unit averages errors of the first and second converted data by digital processing to detect an A/D conversion error, and feeds back a detection result to the A/D conversion unit as a control value to perform voltage control.

Abstract: An analog-to-digital conversion device which converts an analog input signal into a digital signal and output it includes a signal characteristic detection unit for detecting a predetermined characteristic of the input signal; a control signal generation unit for setting a resolution based on the signal characteristic detected by the signal characteristic detection unit, generating a control signal that indicates only an operation required for performing the analog-to-digital conversion at the resolution, and outputting it; and an analog-to-digital conversion unit for restricting the operation based on the control signal and converting the input signal into the digital signal at the set resolution.

Abstract: A non-linear effect of a rectifier element is enhanced, an input amplitude is increased by further taking advantage of a resonance circuit, and a rectification efficiency of a rectifier circuit for detection is improved, so that the gain of an amplifier circuit at a latter stage can be set low. RF input terminals 101, 102 are applied with signals at phases opposite to each other. A signal at terminal 102 is applied to a gate of transistor M1 through capacitor C3, and a signal at terminal 101 is applied to node N1 connected with a source of transistor M1 and a gate and a drain of transistor M2 through capacitor C1. 301, 302 designate terminals applied with DC biases, and L1, C15 and L2, C16 are series resonance circuits. Half-wave double voltage rectifier circuits comprised of M1, M2, C1-C3, R1 are connected in cascade at a plurality of stages.

Abstract: Provided is an electronic circuit system which facilitates skew timing adjustment while preventing increase of power consumption. An electronic circuit system includes: a track hold circuit module formed by a hierarchical tree structure of track hold circuits which can track-hold an analog value of an analog signal; and a control signal generation module which supplies an operation control signal to each of the track hold circuits in the hierarchical tree structure. In the hierarchical tree structure, the number of track hold circuits of each of the hierarchies is stepwise changed from the first hierarchy of the input side to which an analog signal is inputted, toward the final hierarchy of the final output side as the number of hierarchies is increased.

Abstract: An A/D conversion unit performs an A/D conversion operation twice during a hold period of an analog value. In a first conversion operation, the A/D conversion unit compares the analog value with a first reference voltage and outputs a comparison result as first converted data. In a second conversion operation, the A/D conversion unit compares the analog value with a second reference voltage and outputs a comparison result as second converted data. The second reference voltage is a voltage obtained by adding or subtracting a minimum resolution voltage to or from the first reference voltage. A digital processing unit averages errors of the first and second converted data by digital processing to detect an A/D conversion error, and feeds back a detection result to the A/D conversion unit as a control value to perform voltage control.

Abstract: An analog-to-digital conversion device which converts an analog input signal into a digital signal and output it includes a signal characteristic detection unit for detecting a predetermined characteristic of the input signal; a control signal generation unit for setting a resolution based on the signal characteristic detected by the signal characteristic detection unit, generating a control signal that indicates only an operation required for performing the analog-to-digital conversion at the resolution, and outputting it; and an analog-to-digital conversion unit for restricting the operation based on the control signal and converting the input signal into the digital signal at the set resolution.

Abstract: To adequately perform sampling, a receiving device that solves problems that involve an increase in circuit area and an increase in cost, is provided. A/D converter 2 samples a coherent signal that is an analog signal in synchronization with a sampling clock signal so as to convert the analog signal into a digital signal. DSP 3 demodulates the digital signal converted by A/D converter 2 and computes a phase of the sampling clock signal in which an error rate of the digital signal is the minimum based on the demodulated digital signal. Sampling clock extraction circuit 4 extracts a clock signal having a symbol rate of the coherent signal therefrom. Phase adjustment circuit 5 adjusts the phase of the clock signal extracted by sampling clock extraction circuit 4 to the phase computed by DSP 3 and generates a clock signal having the adjusted phase as the sampling clock signal.