Patents by Inventor Tomoyuki Yamase

Tomoyuki Yamase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8015328
    Abstract: An information storage device includes a storage that stores transfer data from an information processing device, the information storage device being removably connected to the information processing device, a switch unit that switches a data transfer mode of the information processing device in accordance with manipulation by a user, and a controller that controls the information processing device to transfer data in a mode in which data temporarily stored in a data storing area is transferred to the storage or in a mode in which data is transferred to the storage without being temporarily stored in the data storing area in accordance with the selection of the data transfer mode by the switch unit.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: September 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Isao Sakakida, Yoshinori Horiguchi, Yuu Yamaguchi, Orie Tsuzuki, Noriaki Matsuno, Tomonobu Kurihara, Tadashi Maeda, Tomoyuki Yamase
  • Publication number: 20110204927
    Abstract: Provided is an electronic circuit system which facilitates skew timing adjustment while preventing increase of power consumption. An electronic circuit system includes: a track hold circuit module formed by a hierarchical tree structure of track hold circuits which can track-hold an analog value of an analog signal; and a control signal generation module which supplies an operation control signal to each of the track hold circuits in the hierarchical tree structure. In the hierarchical tree structure, the number of track hold circuits of each of the hierarchies is stepwise changed from the first hierarchy of the input side to which an analog signal is inputted, toward the final hierarchy of the final output side as the number of hierarchies is increased.
    Type: Application
    Filed: November 2, 2009
    Publication date: August 25, 2011
    Inventors: Tomoyuki Yamase, Hidemi Noguchi
  • Publication number: 20110121864
    Abstract: The nonlinearity effect of a rectifying element is enhanced, and further a resonant circuit is used to enlarge the input amplitude. Furthermore, the rectifying efficiency of a detection rectifier circuit is enhanced, thereby allowing the gain of an amplifier circuit in the following stage to be set to a low value. Signals having mutually opposite phases are inputted to RF input terminals (101,102). The signal at the terminal (102) is then inputted to the gate of a transistor (M1) via a capacitor (C3), while the signal at the terminal (101) is then inputted, via a capacitor (C1), to a node (N1) to which the source of the transistor (M1) and the gate and drain of a transistor (M2) are connected, whereby a capacitor (C2) is charged with a half-wave voltage-doubled rectified current. DC biases are inputted to terminals (301,302). There are formed series resonant circuits (L1,C15;L2,C16). A plurality of half-wave voltage-doubled rectifier circuits (M1,M2,C1-C3,R1) are connected in cascade.
    Type: Application
    Filed: April 5, 2007
    Publication date: May 26, 2011
    Applicant: NEC Corporation
    Inventors: Tadashi Maeda, Tomoyuki Yamase
  • Patent number: 7873139
    Abstract: A signal processing device includes a detecting part that detects intensity of an input signal, a timer part that includes a time constant circuit and measures time based on a time constant of the time constant circuit, and a determination circuit that counts the number of times of switching of the input signal detected by the detecting part within the time measured by the time constant circuit.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: January 18, 2011
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Noriaki Matsuno, Yoshinori Horiguchi, Yuu Yamaguchi, Orie Tsuzuki, Tomonobu Kurihara, Isao Sakakida, Tadashi Maeda, Tomoyuki Yamase
  • Patent number: 7821334
    Abstract: The present invention is aimed at realizing an amplifying circuit whose chip size is prevented from being significantly increased even if the number of compatible frequencies increases, and which has a wide dynamic range when it operates under a low voltage.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Tadashi Maeda, Tomoyuki Yamase
  • Patent number: 7663394
    Abstract: A variation of a threshold of diode-connected transistors is compensated for to maintain a constant rectification efficiency of a rectifier circuit, thereby enabling stable detection of a start signal. A constant voltage is applied to DC bias terminal 103 of cascaded half-wave voltage doubler rectifier circuits (including MOS transistors M1 to M4 and capacitors C1 to C4) forming a rectifier circuit, and a voltage equal to the sum of the constant voltage applied to DC bias terminal 103 and a variation ?Vt of a threshold voltage of the MOS transistors is applied to DC bias terminal 104 of cascaded half-wave voltage doubler rectifier circuits (including MOS transistors M5 to M8 and capacitors C5 to C8) forming a bias circuit.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: February 16, 2010
    Assignee: NEC Corporation
    Inventors: Tomoyuki Yamase, Tadashi Maeda
  • Publication number: 20090245454
    Abstract: A signal processing device includes a detecting part that detects intensity of an input signal, a timer part that includes a time constant circuit and measures time based on a time constant of the time constant circuit, and a determination circuit that counts the number of times of switching of the input signal detected by the detecting part within the time measured by the time constant circuit.
    Type: Application
    Filed: March 30, 2009
    Publication date: October 1, 2009
    Applicants: NEC Electronics Corporation, NEC Corporation
    Inventors: Noriaki Matsuno, Yoshinori Horiguchi, Yuu Yamaguchi, Orie Tsuzuki, Tomonobu Kurihara, Isao Sakakida, Tadashi Maeda, Tomoyuki Yamase
  • Publication number: 20090187688
    Abstract: An information storage device includes a storage that stores transfer data from an information processing device, the information storage device being removably connected to the information processing device, a switch unit that switches a data transfer mode of the information processing device in accordance with manipulation by a user, and a controller that controls the information processing device to transfer data in a mode in which data temporarily stored in a data storing area is transferred to the storage or in a mode in which data is transferred to the storage without being temporarily stored in the data storing area in accordance with the selection of the data transfer mode by the switch unit.
    Type: Application
    Filed: January 9, 2009
    Publication date: July 23, 2009
    Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Isao Sakakida, Yoshinori Horiguchi, Yuu Yamaguchi, Orie Tsuzuki, Noriaki Matsuno, Tomonobu Kurihara, Tadashi Maeda, Tomoyuki Yamase
  • Publication number: 20090010034
    Abstract: A variation of a threshold of diode-connected transistors is compensated for to maintain a constant rectification efficiency of a rectifier circuit, thereby enabling stable detection of a start signal. A constant voltage is applied to DC bias terminal of cascaded half-wave voltage doubler rectifier circuits (including MOS transistors M1 to M4 and capacitors C1 to C4) forming a rectifier circuit, and a voltage equal to the sum of the constant voltage applied to DC bias terminal 103 and a variation ?Vt of a threshold voltage of the MOS transistors is applied to DC bias terminal 104 of cascaded half-wave voltage doubler rectifier circuits (including MOS transistors M5 to M8 and capacitors C5 to C8) forming a bias circuit.
    Type: Application
    Filed: January 11, 2007
    Publication date: January 8, 2009
    Applicant: NEC Corporation
    Inventors: Tomoyuki Yamase, Tadashi Maeda
  • Patent number: 7298215
    Abstract: The present invention provides an amplifying circuit capable of accomplishing high-impedance input/output, and providing a high gain and low power consumption. The amplifier amplifies a signal received through an input terminal, and outputs the signal through an output terminal. A control circuit comprised of the inductors, and the switches turns input/output impedances of the amplifier into a high impedance.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: November 20, 2007
    Assignee: NEC Corporation
    Inventors: Hitoshi Yano, Tomoyuki Yamase, Keiichi Numata, Tadashi Maeda
  • Publication number: 20060033573
    Abstract: The present invention provides an amplifying circuit capable of accomplishing high-impedance input/output, and providing a high gain and low power consumption. The amplifier amplifies a signal received through an input terminal, and outputs the signal through an output terminal. A control circuit comprised of the inductors, and the switches turns input/output impedances of the amplifier into a high impedance.
    Type: Application
    Filed: December 3, 2003
    Publication date: February 16, 2006
    Inventors: Hitoshi Yano, Tomoyuki Yamase, Keiichi Numata, Tadashi Maeda