Abstract: A method for forming a contact hole in a silicon oxide layer formed over a silicon nitride layer and a substrate performs an etching process with an etchant, C4F8/Ar or C4F8/C2F6/Ar, on an inductively coupled plasma etcher. The inductively coupled plasma etcher contains a chamber, a ring, and a roof. The etchant used in the etching process is controlled by conditions that include a C4F8 flow of about 10 to 20 sccm, a CO flow of less than about 100 sccm, and an Ar flow of about 50 to 500 sccm. In the meantime, the conditions of the inductively coupled plasma etcher include a roof temperature of about 150 to 300 ° C., a ring temperature of about 150 to 400 ° C., and a pressure within the chamber of about 4 to 50 mtorr. By performing a plasma etching process under the foregoing conditions, a properly profiled contact hole is obtained.

Abstract: The present invention relates to a method of forming a contact hole on the semiconductor wafer. The semiconductor wafer comprises, in ascending order, a substrate, a silicon nitride layer, a silicon oxide layer, and a photo-resist layer. There is a hole in the photo-resist layer. The method comprises: (1) performing a first anisotropic etching process in a downward direction to remove the silicon oxide layer under the hole down to the surface of the silicon nitride layer to form a recess; (2) performing an in-situ plasma cleaning process to entirely remove the polymer material remaining at the bottom of the recess; (3) performing an in-situ second anisotropic etching process in a downward direction to remove the silicon nitride layer from the bottom of the recess down to the surface of the substrate to form the contact hole; (4) performing another in-situ cleaning process to entirely remove the polymer material remaining at the bottom of the contact hole.

Abstract: A seasoning process for an etcher which is performed before etching a dielectric layer to expose a metal silicide layer. The seasoning process includes the first plasma sputtering process and the second plasma sputtering process. A wafer containing the metal silicide layer thereon is placed in the etcher with an etchant and the first plasma sputtering process is performed. Several silicon wafers are successively placed in the etcher to perform the second plasma sputtering process.

Abstract: An etching method used in the high density plasma etching system to etch a silicon oxide dielectric layer to form openings of different depths. The method uses a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, and Ar as an etching gas source to etch the silicon oxide dielectric layer, forming a plurality of openings of a first depth. A mixture of C.sub.4 H.sub.8, CO, and Ar is used as an etching gas source to etch the silicon oxide dielectric layer exposed by the first opening, so that the opening is deepened to the second depth. Using a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, CO, and Ar as the etching gas source, the silicon oxide dielectric layer exposed by the opening is etched, so that the openings are deepened to the third depth and the fourth depth.

Abstract: A multilevel contact etching method to form a contact opening is provided. The method contains using an inductively coupled plasma (ICP) etcher to produce a high plasma density condition. The plasma gas etchant is composed of C.sub.4 F.sub.8 /CH.sub.2 F.sub.2 /CO/Ar with a ratio of 3:4:12:80 so that silicon nitride can be selectively etched while the silicon and silicide are not etched. Each content ratio of the plasma gas etchant allows a variance of about 20%. Wall temperature of the ICP etcher is about 100.degree. C.-300.degree. C. A cooling system for a wafer pad is about -20.degree. C.-20.degree. C. Chamber pressure is about 5-100 mtorr. Bias power on the wafer pad is about 1000 W-3000 W. Source power of an inductance coil is about 500 W-3000 W.

Abstract: An oxide etching method using low-medium density plasma includes a first etching step to pre-etch the oxide layer with low etching selectivity etchant to pre-form a contact opening and a monitoring opening. The low etching selectivity etchant can also etch the photoresist layer and the photoresist reaction residue. Then, a second etching with high etching selectivity on the oxide is performed to completely form the contact opening with a SAC property and the monitoring opening. The openings expose the substrate.

Abstract: A computer system having a computer model of a Finite State Machine (FSM). The computer system includes a processor coupled to receive and manipulate the computer model, and a memory. The memory includes a computer model. The computer model includes, a first set of inputs, a first set of delayed inputs, a first set of outputs and a first set of delayed outputs. The computer model has a first output of the first set of outputs corresponding to a first input of the first set of inputs, a first delayed input of the first set of inputs and a first delayed output of the first set of delayed outputs.