Patents by Inventor Tong Yu

Tong Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080104680
    Abstract: Methods, systems, and products for local blade server security are provided. Embodiments include extracting authentication information for a local user from a USB keydrive inserted in the chassis of the blade server; comparing the extracted authentication information with predetermined authentication credentials; and granting access to one or more resources on the blade server if the extracted authentication information matches the predetermined authentication credentials; and denying access to one or more resources on the blade server if the extracted authentication information does not match the predetermined authentication credentials.
    Type: Application
    Filed: October 2, 2006
    Publication date: May 1, 2008
    Inventors: Gregg K. Gibson, Eric R. Kern, Michael S. Rollins, Janae V. Simons, David R. Woodham, Tong Yu
  • Publication number: 20080098071
    Abstract: A method, article, and system to implement software for enabling recipients to unsubscribe from an electronic message thread, in which case, the electronic message will not be delivered into the recipient's box, and therefore will not be utilizing any of the recipient's inbox space. The message server will hold the electronic message, where the recipient can access it if they choose. Also, other recipients who choose to reply-to-all will be notified of recipients who have unsubscribed, and will be able to then send the electronic message to the unsubscribed recipient if they are a required viewer.
    Type: Application
    Filed: October 23, 2006
    Publication date: April 24, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Angela Richards Jones, Tong Yu
  • Publication number: 20080013269
    Abstract: A notebook computer is disclosed. The notebook computer includes a display unit, a main unit and a combination lock. The combination lock is mounted on the main unit, includes dials exposed on a front wall of the main unit, and defines a latch hole therein. A hook corresponding to the latch hole is mounted on the display unit. The combination lock is a reliable protection means for preventing information leakage when a user leaves the notebook computer for a while.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 17, 2008
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: SHIH-FANG WONG, WEN-HAW TSENG, LEI-TONG YU, LI LI, XIU-XUAN LI, YUN-TAO GAO
  • Patent number: 7319074
    Abstract: The present invention provides a method of defining polysilicon patterns. The method forms a polysilicon layer on a substrate, and a patterned mask on the polysilicon layer. Then, a first etching process is performed to remove a portion of the polysilicon layer not covered by the mask, thus forming a plurality of cavities in the polysilicon layer. A strip process is performed to strip the mask utilizing gases excluding O2. Finally, a second etching process is performed to remove a portion of the polysilicon layer, thus extending the plurality of cavities down to a surface of the substrate.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: January 15, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Pei-Yu Chou, Tong-Yu Chen
  • Publication number: 20070209448
    Abstract: An apparatus for testing bending strength is provided. The apparatus includes a frame, a motor, and a control part. The frame includes an impingement board. The motor includes a piston. A piston head is mounted on an end of the piston for impacting the impingement board. The piston head defines a space configured for receiving a hand-held device. The control part is for controlling the piston to move up and down repeatedly. The apparatus can be used to test a hand-held device's bending strength conveniently.
    Type: Application
    Filed: February 27, 2007
    Publication date: September 13, 2007
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Shih-Fang Wong, Wen-Haw Tseng, Li Li, Lei-Tong Yu, Xiu-Xuan Li, Yun-Tao Gao
  • Publication number: 20070193364
    Abstract: An apparatus for testing bending strength is provided. The apparatus includes a frame, a load-supporting platform, a motor, and a control part. The load-supporting platform is mounted on the frame. The load-supporting platform includes a vessel configured for receiving a hand-held device. The motor includes a piston. A piston head is mounted on one end of the piston for impacting the vessel. The piston head includes a convex face oriented to face the vessel. The control part is configured for controlling the piston to move up and down repeatedly. The apparatus can be used to test a hand-held device's bending strength conveniently.
    Type: Application
    Filed: December 19, 2006
    Publication date: August 23, 2007
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Shih-Fang Wong, Wen-Haw Tseng, Lei-Tong Yu, Xiu-Xuan Li, Li Li, Yun-Tao Gao
  • Patent number: 7254759
    Abstract: A method for semiconductor defect detection, applied to a wafer test in a semiconductor process. A defect test is implemented for generating redundant information. an abnormal test implemented for generating a first FBM. The redundant information is converted to a second FBM. The first and second FBMs are compared, thereby generating a third FBM according to comparison results.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: August 7, 2007
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Tong-Yu Liu, Yen-Sheng Chang
  • Publication number: 20060294313
    Abstract: A system and method of remote media cache optimization for use with multiple processing units. The present invention discloses a data processing system that includes multiple processing units, a storage device, and a storage device adapter for coupling the storage device to the multiple processing units. The data processing system also includes a cache coupled to the storage device. The cache includes a data partition for storing data retrieved from the storage device and multiple sense data partitions. Each of the multiple sense partitions correspond to a respective one of the multiple processing units. In response to the storage device receiving a first command from a first processing unit, the storage device issues a response to the command and the storage device adapter stores sense data corresponding to the first command in a first sense data partition.
    Type: Application
    Filed: June 23, 2005
    Publication date: December 28, 2006
    Applicant: International Business Machines Corporation
    Inventors: Brooks Johnston, Eric Kern, Tong Yu
  • Publication number: 20060281325
    Abstract: The present invention provides a method of defining polysilicon patterns. The method forms a polysilicon layer on a substrate, and a patterned mask on the polysilicon layer. Then, a first etching process is performed to remove a portion of the polysilicon layer not covered by the mask, thus forming a plurality of cavities in the polysilicon layer. A strip process is performed to strip the mask utilizing gases excluding O2. Finally, a second etching process is performed to remove a portion of the polysilicon layer, thus extending the plurality of cavities down to a surface of the substrate.
    Type: Application
    Filed: June 13, 2005
    Publication date: December 14, 2006
    Inventors: Pei-Yu Chou, Tong-Yu Chen
  • Publication number: 20060143550
    Abstract: A method for semiconductor defect detection, applied to a wafer test in a semiconductor process. A defect test is implemented for generating redundant information. an abnormal test implemented for generating a first FBM. The redundant information is converted to a second FBM. The first and second FBMs are compared, thereby generating a third FBM according to comparison results.
    Type: Application
    Filed: August 15, 2005
    Publication date: June 29, 2006
    Inventors: Tong-Yu Liu, Yen-Sheng Chang
  • Patent number: 6972259
    Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: December 6, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • Publication number: 20050110152
    Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.
    Type: Application
    Filed: December 23, 2004
    Publication date: May 26, 2005
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • Publication number: 20040250966
    Abstract: An actuating mechanism for angles of light of a vertical curtain, and more particularly, an actuating mechanism for adjusting angles of incoming light of a curtain having vertical slats, includes a rotating gear indirectly disposed between an interlocking gear and a driving gear thereof. The driving gear is disposed with deviation. Using an elastic clutch escape function and various diameters of the driving gear, the aforesaid structure is able to adapt to different torsion requirements for full breadth light shielding effects, as well as safe applications.
    Type: Application
    Filed: June 16, 2003
    Publication date: December 16, 2004
    Inventor: Shih-Tong Yu
  • Patent number: 6806182
    Abstract: Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: October 19, 2004
    Assignees: International Business Machines Corporation, Infineon Technologies, AG, United Microelectronics Co.
    Inventors: Darryl Restaino, Shahab Siddiqui, Erdem Kaltalioglu, Delores Bennett, Chih-Chih Liu, Hsueh-Chung Chen, Tong-Yu Chen, Gwo-Shii Yang, Chiung-Sheng Hsiung
  • Patent number: 6750129
    Abstract: A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: June 15, 2004
    Assignee: Infineon Technologies AG
    Inventors: Gwo-Shii Yang, Jen Kon Chen, Hsueh-Chung Chen, Hans-Joachim Barth, Chiung-Sheng Hsiung, Chih-Chien Liu, Tong-Yu Chen, Yi-hsiung Lin, Chih-Chao Yang
  • Publication number: 20040092091
    Abstract: A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 13, 2004
    Inventors: Gwo-Shii Yang, Jen Kon Chen, Hsueh-Chung Chen, Hans-Joachim Barth, Chiung-Sheng Hsiung, Chih-Chien Liu, Tong-Yu Chen, Yi-hsiung Lin, Chih-Chao Yang
  • Publication number: 20030207559
    Abstract: Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.
    Type: Application
    Filed: May 1, 2002
    Publication date: November 6, 2003
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, Infineon Technologies North America Corp., United Microelectronics Co.
    Inventors: Darryl Restaino, Shahab Siddiqui, Erdem Kaltalioglu, Delores Bennett, C. C. Liu, Hsueh-Chung Chen, Tong-Yu Chen, Gwo-Shii Yang, Chiung-Sheng Hsiung
  • Patent number: 6638871
    Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers. A cap layer, a low-k dielectric layer, a metal hard mask layer and a hard mask layer are formed in sequence on a provided substrate with metal wires. After patterning the metal hard mask layer and the hard mask layer to form a first opening, a fluid filling material layer is formed on the hard mask layer and fills the first opening. Using a patterned photoresist layer as a mask to define the filling material layer and the low-k dielectric layer, a second opening is obtained. After removing the photoresist layer along with the filling material layer, a damascene opening is formed by using the metal hard mask and the hard mask layers as a mask and the cap layer as an etching stop layer.
    Type: Grant
    Filed: January 10, 2002
    Date of Patent: October 28, 2003
    Assignee: United Microlectronics Corp.
    Inventors: Chin-Jung Wang, Tong-Yu Chen
  • Publication number: 20030199132
    Abstract: A method for forming a damascene opening in a polymer-based dielectric layer is introduced. The method includes providing a substrate, which has also a conductive structure layer and a polymer-based dielectric layer formed thereon already. The polymer-based dielectric layer is uniformly hardened by a thermal treatment. A mask layer is formed on the polymer-based dielectric layer. The mask layer and the polymer-based dielectric layer are patterned to form an opening. The opening exposes a surface of the polymer-based dielectric layer. The exposed surface of the polymer-based dielectric layer is further hardened by a local hardening process. The local hardening process includes using an irradiation source of a high energy light beam, electron beam or ion beam to proceed the local hardening. The irradiation source can be incident onto the substrate by vertical angle or inclining angle. The substrate can also be rotated.
    Type: Application
    Filed: April 25, 2003
    Publication date: October 23, 2003
    Inventors: Hsueh-Chung Chen, Tong-Yu Chen, Chih-Chien Liu, Chingfu Lin
  • Publication number: 20030129844
    Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.
    Type: Application
    Filed: November 13, 2002
    Publication date: July 10, 2003
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Jung Wang, Tong-Yu Chen