Patents by Inventor Tong Yu

Tong Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Ventilation system
    Patent number: 9415712
    Abstract: The present invention is drawn to a ventilation system for a “climate object”, in particular all components with which the user of a vehicle may come in contact in a passenger compartment such as, for example, a steering mechanism for a vehicle, a dashboard, an armrest, a door paneling, a seat cover, a heating blanket, a padding, a cover or a seat, all which include at least one air flow device to guide air through the climate object.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: August 16, 2016
    Assignee: GENTHERM GMBH
    Inventors: Andreas Stoll, Jonathan Zhang, Thomas Fries, Eric (Tong) Yu, Denise Philipp
  • Method and apparatus for cross domain and cross-layer event correlation
    Patent number: 9413685
    Abstract: Methods and apparatus to provide a cloud computing system having cross domain event correlation. In one embodiment, a first alert is received in a first domain of the system domains and a second alert in a second domain of the system domains, the first and second alerts caused by an event. A topology of the system is determined and connectivity matching is performed to identify connections between a port in the first domain and a port in the second domain. Identify matching, using unique identifiers for domain components, is performed to determine that a first component in the first domain associated with the first alert is the same component as a second component associated with the second alert in the second domain for cross domain event correlation.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: August 9, 2016
    Assignee: EMC Corporation
    Inventors: Cheuk Lam, Tong Yu, David Moran, Pavan Banda, Lida He
  • SYSTEM AND METHOD FOR UNFILTERING FILTERED STATUS MESSAGES
    Publication number: 20160191439
    Abstract: An approach for unfiltering a filtered electronic communication is provided. In one aspect, a computer system receives filtered electronic communication, wherein the filtered electronic communication is a status message. Moreover, the computer system determines a requestor of the filtered electronic communication. The computer system also detects an attempt made to communicate with the requestor. Furthermore, the computer system unfilters, in response to the attempt, the filtered electronic communication.
    Type: Application
    Filed: March 4, 2016
    Publication date: June 30, 2016
    Inventors: Al Chakra, Michael S. Thomason, Tong Yu
  • Semiconductor structure and method of forming a harmonic-effect-suppression structure
    Patent number: 9378998
    Abstract: A method of forming a harmonic-effect-suppression structure is disclosed. The method includes: providing a semiconductor substrate having a base semiconductor substrate, a buried dielectric on the base semiconductor substrate, and a surface semiconductor layer on the buried dielectric. Next, a deep trench is formed extending through the surface semiconductor layer and the buried dielectric into the base semiconductor substrate, a silicon layer is formed within a lower portion of the deep trench, the silicon layer allowed to have a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate, and a dielectric layer is formed within the deep trench and on the silicon layer.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: June 28, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Kuo-Yuh Yang
  • System and method for unfiltering filtered status messages
    Patent number: 9319361
    Abstract: An approach for unfiltering a filtered electronic communication is provided. In one aspect, a computer system receives filtered electronic communication, wherein the filtered electronic communication is a status message. Moreover, the computer system determines a requestor of the filtered electronic communication. The computer system also detects an attempt made to communicate with the requestor. Furthermore, the computer system unfilters, in response to the attempt, the filtered electronic communication.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: April 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Al Chakra, Michael S. Thomason, Tong Yu
  • Method and apparatus for performance data transformation in a cloud computing system
    Patent number: 9298582
    Abstract: Methods and apparatus to provide performance data transformation in a cloud computing system. In one embodiment, the system performs data transformation with information from a configuration subsystem, to generate metrics for network layer, storage layer, compute layer, and logical components.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: March 29, 2016
    Assignee: EMC Corporation
    Inventors: Lianlai Zhang, Lida He, Jamel Hammouda, Tong Yu, Cheuk Lam
  • Method of forming trench in semiconductor substrate
    Patent number: 9214384
    Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 15, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Semiconductor structure having material layers which are level with each other and manufacturing method thereof
    Patent number: 9105590
    Abstract: A semiconductor structure is provided in the present invention. The semiconductor structure includes a substrate, a first material layer and a second material layer. A trench region is defined on the substrate. The trench region includes two separated first regions and a second region, wherein the second region is adjacent to and between the two first regions. The first material layer is disposed on the substrate outside the trench region. The second material layer is disposed in the second region and is level with the first material layer.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: August 11, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Tong-Yu Chen
  • Semiconductor structure and method of forming a harmonic-effect-suppression structure
    Publication number: 20150221543
    Abstract: A method of forming a harmonic-effect-suppression structure is disclosed. The method includes: providing a semiconductor substrate having a base semiconductor substrate, a buried dielectric on the base semiconductor substrate, and a surface semiconductor layer on the buried dielectric. Next, a deep trench is formed extending through the surface semiconductor layer and the buried dielectric into the base semiconductor substrate, a silicon layer is formed within a lower portion of the deep trench, the silicon layer allowed to have a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate, and a dielectric layer is formed within the deep trench and on the silicon layer.
    Type: Application
    Filed: April 15, 2015
    Publication date: August 6, 2015
    Inventors: Tong-Yu Chen, Kuo-Yuh Yang
  • SYSTEM AND METHOD FOR UNFILTERING FILTERED STATUS MESSAGES
    Publication number: 20150188864
    Abstract: An approach for unfiltering a filtered electronic communication is provided. In one aspect, a computer system receives filtered electronic communication, wherein the filtered electronic communication is a status message. Moreover, the computer system determines a requestor of the filtered electronic communication. The computer system also detects an attempt made to communicate with the requestor. Furthermore, the computer system unfilters, in response to the attempt, the filtered electronic communication.
    Type: Application
    Filed: March 13, 2015
    Publication date: July 2, 2015
    Inventors: Al Chakra, Michael S. Thomason, Tong Yu
  • PATTERNED STRUCTURE OF SEMICONDUCTOR DEVICE
    Publication number: 20150179652
    Abstract: A patterned structure of a semiconductor device includes a substrate, at least a first patterned structure, and at least a second patterned structure. The first patterned structure is a single-layered structure, and the second patterned structure is a multi-layered structure. The width of the second patterned structure is greater than the width of the first patterned structure.
    Type: Application
    Filed: March 5, 2015
    Publication date: June 25, 2015
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF
    Publication number: 20150171194
    Abstract: A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.
    Type: Application
    Filed: March 3, 2015
    Publication date: June 18, 2015
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Semiconductor structure and method of forming a harmonic-effect-suppression structure
    Patent number: 9048285
    Abstract: A semiconductor structure includes a SOI/BOX semiconductor substrate, a device, a deep trench, a silicon layer, and a dielectric layer. The deep trench is adjacent to the device and extends through a shallow trench isolation layer within the SOI layer and the BOX layer and into the base semiconductor substrate. The silicon layer is disposed within a lower portion of the deep trench. The silicon layer has a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate. The dielectric layer is disposed within the deep trench and on the silicon layer. The deep trench can be formed before or after formation of an interlayer dielectric.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: June 2, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Kuo-Yuh Yang
  • System and method for unfiltering filtered status messages
    Patent number: 9026600
    Abstract: An approach for unfiltering a filtered electronic communication is provided. In one aspect, a computer system receives filtered electronic communication, wherein the filtered electronic communication is a status message. Moreover, the computer system determines a requestor of the filtered electronic communication. The computer system also detects an attempt made to communicate with the requestor. Furthermore, the computer system unfilters, in response to the attempt, the filtered electronic communication.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Al Chakra, Michael S. Thomason, Tong Yu
  • Method of Forming Trench in Semiconductor Substrate
    Publication number: 20150111385
    Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.
    Type: Application
    Filed: December 24, 2014
    Publication date: April 23, 2015
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Field effect transistor and manufacturing method thereof
    Patent number: 9012975
    Abstract: A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: April 21, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Patterned structure of semiconductor device and fabricating method thereof
    Patent number: 9006107
    Abstract: A method for fabricating a patterned structure in a semiconductor device is provided. First, a substrate with a first region and a second region is provided. Then, a plurality of sacrificial patterns is respectively formed within the first region and the second region. A first spacer is then formed on the sidewalls of each of the sacrificial patterns followed by forming a mask layer to cover the sacrificial patterns located within the first region. Finally, the first spacer exposed from the mask layer is trimmed to be a second spacer and the mask layer is then removed.
    Type: Grant
    Filed: March 11, 2012
    Date of Patent: April 14, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • Method for fabricating MOS device
    Patent number: 8946031
    Abstract: A method for fabricating a MOS device is described. A first hard mask layer is formed over a substrate. The first hard mask layer is patterned and a portion of the substrate removed to form a first patterned hard mask, and a fin structure surrounded by a trench and extending in a first direction. An insulating layer is formed at the trench bottom. A gate conductive layer is formed on the insulating layer, extending in a second direction. A first implant process is performed using the first patterned hard mask as a mask to form first S/D extension regions in the sidewalls of the fin structure. The first patterned hard mask is removed to expose the top of the fin structure, and then a second implant process is performed to form second S/D extension region therein.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: February 3, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • Method of forming trench in semiconductor substrate
    Patent number: 8946078
    Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: February 3, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Semiconductor structure and method of forming a harmonic-effect-suppression structure
    Publication number: 20150001670
    Abstract: A semiconductor structure includes a SOI/BOX semiconductor substrate, a device, a deep trench, a silicon layer, and a dielectric layer. The deep trench is adjacent to the device and extends through a shallow trench isolation layer within the SOI layer and the BOX layer and into the base semiconductor substrate. The silicon layer is disposed within a lower portion of the deep trench. The silicon layer has a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate. The dielectric layer is disposed within the deep trench and on the silicon layer. The deep trench can be formed before or after formation of an interlayer dielectric.
    Type: Application
    Filed: July 1, 2013
    Publication date: January 1, 2015
    Inventors: Tong-Yu Chen, Kuo-Yuh Yang