Patents by Inventor Tong Zhao

Tong Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7983011
    Abstract: A TMR read head with improved voltage breakdown is formed by laying down the AP1 layer as two or more layers. Each AP1 sub-layer is exposed to a low energy plasma for a short time before the next layer is deposited. This results in a smooth surface, onto which to deposit the tunneling barrier layer, with no disruption of the surface crystal structure of the completed AP1 layer.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: July 19, 2011
    Assignee: Headway Technologies, Inc.
    Inventors: Tong Zhao, Chyu-Jiuh Torng, Hui-Chuan Wang
  • Patent number: 7978439
    Abstract: An insertion layer is provided between an AFM layer and an AP2 pinned layer in a GMR or TMR element to improve exchange coupling properties by increasing Hex and the Hex/Hc ratio without degrading the MR ratio. The insertion layer may be a 1 to 15 Angstrom thick amorphous magnetic layer comprised of at least one element of Co, Fe, or Ni, and at least one element having an amorphous character selected from B, Zr, Hf, Nb, Ta, Si, or P, or a 1 to 5 Angstrom thick non-magnetic layer comprised of Cu, Ru, Mn, Hf, or Cr. Preferably, the content of the one or more amorphous elements in the amorphous magnetic layer is less than 40 atomic %. Optionally, the insertion layer may be formed within the AP2 pinned layer. Examples of an insertion layer are CoFeB, CoFeZr, CoFeNb, CoFeHf, CoFeNiZr, CoFeNiHf, and CoFeNiNbZr.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: July 12, 2011
    Assignee: Headway Technologies, Inc.
    Inventors: Kunliang Zhang, Hui-Chuan Wang, Tong Zhao, Min Li
  • Patent number: 7950136
    Abstract: A process to manufacturing a TMR read head with improved voltage breakdown is performed by laying down the AP1 layer as two or more layers. Each AP1 sub-layer is exposed to a low energy plasma for a short time before the next layer is deposited. This results in a smooth surface, onto which to deposit the tunneling barrier layer, with no disruption of the surface crystal structure of the completed AP1 layer.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: May 31, 2011
    Assignee: Headway Technologies, Inc.
    Inventors: Tong Zhao, Chyu-Jiuh Torng, Hui-Chuan Wang
  • Patent number: 7916513
    Abstract: A data storage device comprising a ferroelectric layer, a perovskite structure, and at least one sensor, where the perovskite structure has a polarity discontinuity configured to generate capacitance voltages in the perovskite structure based on polarization charges of the ferroelectric material, and where the at least one sensor is configured to read the capacitance voltages from the perovskite structure.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: March 29, 2011
    Assignee: Seagate Technology LLC
    Inventors: Shan Hu, Tong Zhao, Florin Zavaliche, Joachim Ahner, Stephen John Wrazien, Martin Gerard Forrester
  • Publication number: 20110054026
    Abstract: Antimicrobial compositions are provided comprising a pharmaceutically acceptable organic acid and a pharmaceutically acceptable surfactant. This synergistic combination allows compositions to be formulated at low concentrations that have efficacy in reducing bacterial counts by greater than 3 log within 5 minutes of contact while preserving the organoleptic properties of treated foods, including fresh produce. As shown in FIG. 1C the efficacy of six different compositions (A. 3% levulinic acid plus 2% SDS; B. 2% levulinic acid plus 1% SDS; C. 0.5% levulinic acid plus 0.05% SDS; D. 3% levulinic acid; E. 2% SDS and F. water) were tested for their ability to kill spores of Bacillus anthracis Sterne after 45 minutes of contact.
    Type: Application
    Filed: May 21, 2009
    Publication date: March 3, 2011
    Inventors: Michael Patrick Doyle, Tong Zhao
  • Publication number: 20110038246
    Abstract: The presently disclosed technology teaches an improved voltage pattern for conductive tips utilized as moveable top electrodes for writing data bits into ferroelectric media. A conductive tip is dragged in contact or near contact with a ferroelectric surface forming a moveable top electrode on a ferroelectric media disk. A metallic film is deposited onto a bottom-side of the ferroelectric media forming a conductive bottom electrode. Applying electrical voltage pulses between the conductive tip and the bottom electrode induces polarization switching of the ferroelectric media under the head. The improved voltage pattern incorporates positive and negative overshoot voltages to induce a polarization switch in the ferroelectric media and positive and negative drag voltages to expand a polarized region on the ferroelectric media. Potential benefits of the improved voltage pattern include reduced cross-track blooming and reduced along-track blooming resulting in a more uniform track width and bit series length.
    Type: Application
    Filed: August 12, 2009
    Publication date: February 17, 2011
    Applicant: Seagate Technology, LLC
    Inventors: Andreas Karl Roelofs, Tong Zhao, Martin Gerard Forrester
  • Patent number: 7876661
    Abstract: An apparatus that provides for non-destructive readback of a ferroelectric material. The apparatus can include a ferroelectric layer with a scannable surface wherein the ferroelectric layer has a compensation charge adjacent the scannable surface. The apparatus also can include an electrode adjacent the scannable surface to sense the compensation charge. A related method is also disclosed.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: January 25, 2011
    Assignee: Seagate Technology LLC
    Inventors: Tong Zhao, Martin G. Forrester, Florin Zavaliche, Dierk Guenter Bolten, Andreas Karl Roelofs
  • Patent number: 7861401
    Abstract: A high performance TMR element is fabricated by inserting an oxygen surfactant layer (OSL) between a pinned layer and AlOx tunnel barrier layer in a bottom spin valve configuration. The pinned layer preferably has a SyAP configuration with an outer pinned layer, a Ru coupling layer, and an inner pinned layer comprised of CoFeXBY/CoFeZ wherein x=0 to 70 atomic %, y=0 to 30 atomic %, and z=0 to 100 atomic %. The OSL is formed by treating the CoFeZ layer with oxygen plasma. The AlOx tunnel barrier has improved uniformity of about 2% across a 6 inch wafer and can be formed from an Al layer as thin as 5 Angstroms. As a result, the Hin value can be decreased by ? to about 32 Oe. A dR/R of 25% and a RA of 3 ohm-cm2 have been achieved for TMR read head applications.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: January 4, 2011
    Assignee: Headway Technologies, Inc.
    Inventors: Hui-Chuan Wang, Tong Zhao, Min Li, Kunliang Zhang
  • Publication number: 20100320076
    Abstract: A high performance TMR sensor is fabricated by incorporating a tunnel barrier having a Mg/MgO/Mg configuration. The 4 to 14 Angstroms thick lower Mg layer and 2 to 8 Angstroms thick upper Mg layer are deposited by a DC sputtering method while the MgO layer is formed by a NOX process involving oxygen pressure from 0.1 mTorr to 1 Torr for 15 to 300 seconds. NOX time and pressure may be varied to achieve a MR ratio of at least 34% and a RA value of 2.1 ohm-um2. The NOX process provides a more uniform MgO layer than sputtering methods. The second Mg layer is employed to prevent oxidation of an adjacent ferromagnetic layer. In a bottom spin valve configuration, a Ta/Ru seed layer, IrMn AFM layer, CoFe/Ru/CoFeB pinned layer, Mg/MgO/Mg barrier, CoFe/NiFe free layer, and a cap layer are sequentially formed on a bottom shield in a read head.
    Type: Application
    Filed: August 5, 2010
    Publication date: December 23, 2010
    Inventors: Tong Zhao, Kunliang Zhang, Hui Chuan Wang, Yu-Hsia Chen, Min Li
  • Publication number: 20100304185
    Abstract: A high performance TMR sensor is fabricated by incorporating a tunnel barrier having a Mg/MgO/Mg configuration. The 4 to 14 Angstroms thick lower Mg layer and 2 to 8 Angstroms thick upper Mg layer are deposited by a DC sputtering method while the MgO layer is formed by a NOX process involving oxygen pressure from 0.1 mTorr to 1 Torr for 15 to 300 seconds. NOX time and pressure may be varied to achieve a MR ratio of at least 34% and a RA value of 2.1 ohm-um2. The NOX process provides a more uniform MgO layer than sputtering methods. The second Mg layer is employed to prevent oxidation of an adjacent ferromagnetic layer. In a bottom spin valve configuration, a Ta/Ru seed layer, IrMn AFM layer, CoFe/Ru/CoFeB pinned layer, Mg/MgO/Mg barrier, CoFe/NiFe free layer, and a cap layer are sequentially formed on a bottom shield in a read head.
    Type: Application
    Filed: August 6, 2010
    Publication date: December 2, 2010
    Inventors: Tong Zhao, Kunliang Zhang, Hui Chuan Wang, Yu-Hsia Chen, Min Li
  • Patent number: 7838066
    Abstract: A single annealing process simultaneously creates local areas of ferroelectric imprint that can be used as markers, and areas with low leakage current that exhibit ideal symmetric switching on ferroelectric recording media.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: November 23, 2010
    Assignee: Seagate Technology LLC
    Inventors: Tong Zhao, Andreas Roelofs, Cedric Stephane Bedoya
  • Patent number: 7829963
    Abstract: A MTJ structure is disclosed in which the seed layer is made of a lower Ta layer, a middle Hf layer, and an upper NiFe or NiFeX layer where X is Co, Cr, or Cu. Optionally, Zr, Cr, HfZr, or HfCr may be employed as the middle layer and materials having FCC structures such as CoFe and Cu may be used as the upper layer. As a result, the overlying layers in a TMR sensor will be smoother and less pin dispersion is observed. The Hex/Hc ratio is increased relative to that for a MTJ having a conventional Ta/Ru seed layer configuration. The trilayer seed configuration is especially effective when an IrMn AFM layer is grown thereon and thereby reduces Hin between the overlying pinned layer and free layer. Ni content in the NiFe or NiFeX middle layer is above 30 atomic % and preferably >80 atomic %.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: November 9, 2010
    Assignee: Headway Technologies, Inc.
    Inventors: Hui-Chuan Wang, Kunliang Zhang, Tong Zhao, Min Li
  • Patent number: 7821808
    Abstract: A data storage system comprises first and second storage layers, a reader and a writer. The first storage layer has a first coercive potential and a first polarization. The second storage layer has a second coercive potential that is less than the first coercive potential, and a second polarization that is coupled to the first polarization. The writer performs a write operation in which a write potential is imposed across the first and second storage layers, such that the first coercive potential is exceeded across the first storage layer and the second coercive potential is exceeded across the second storage layer. The reader performs a read operation in which a read potential is imposed across the first and second storage layers, such that the second coercive potential is exceeded across the second storage layer and the first coercive potential is not exceeded across the first storage layer.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: October 26, 2010
    Assignee: Seagate Technology LLC
    Inventors: Tong Zhao, Martin Gerard Forrester, Florin Zavaliche, Joachim Ahner
  • Publication number: 20100247966
    Abstract: The conventional free layer in a TMR read head has been replaced by a composite of two or more magnetic layers, one of which is iron rich The result is an improved device that has a higher MR ratio than prior art devices, while still maintaining free layer softness and acceptable magnetostriction. A process for manufacturing the device is also described.
    Type: Application
    Filed: May 28, 2010
    Publication date: September 30, 2010
    Inventors: Tong Zhao, Hui-Chuan Wang, Chyu-Jiuh Torng
  • Patent number: 7796494
    Abstract: A method of writing to ferroelectric storage medium includes the steps of applying a first write voltage to a ferroelectric layer for writing a first bit in a first polarization direction and applying a second write voltage to the ferroelectric layer for writing a second bit in a second polarization direction opposing the first polarization direction. The first write voltage having a first magnitude, and the second write voltage having a second magnitude being greater than the first magnitude. The ferroelectric layer having a ferroelectric imprint polarization direction, and the first polarization direction being substantially the same as the ferroelectric imprint polarization direction. The ferroelectric medium contains first bits with a first surface area that is substantially equal to second bits surface area. A probe storage apparatus can use this method and ferroelectric medium.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: September 14, 2010
    Assignee: Seagate Technology, LLC
    Inventors: Tong Zhao, Andreas Roelofs, Martin Forrester
  • Patent number: 7792009
    Abstract: A ferroelectric polarization pattern with differing feedback signals. An apparatus including a ferroelectric layer and a polarization pattern configured in the ferroelectric layer to represent position data. The polarization pattern has a first switchable polarization state domain and a second switchable polarization state domain that are both switchable by an applied signal. The first switchable polarization state domain has a first feedback signal in response to the applied signal that is different than a second feedback signal of the second switchable polarization state domain at the applied signal.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: September 7, 2010
    Assignee: Seagate Technology LLC
    Inventors: Florin Zavaliche, Philip George Pitcher, Tong Zhao, Dierk Guenter Bolten
  • Patent number: 7780820
    Abstract: A high performance TMR sensor is fabricated by incorporating a tunnel barrier having a Mg/MgO/Mg configuration. The 4 to 14 Angstroms thick lower Mg layer and 2 to 8 Angstroms thick upper Mg layer are deposited by a DC sputtering method while the MgO layer is formed by a NOX process involving oxygen pressure from 0.1 mTorr to 1 Torr for 15 to 300 seconds. NOX time and pressure may be varied to achieve a MR ratio of at least 34% and a RA value of 2.1 ohm-um2. The NOX process provides a more uniform MgO layer than sputtering methods. The second Mg layer is employed to prevent oxidation of an adjacent ferromagnetic layer. In a bottom spin valve configuration, a Ta/Ru seed layer, IrMn AFM layer, CoFe/Ru/CoFeB pinned layer, Mg/MgO/Mg barrier, CoFe/NiFe free layer, and a cap layer are sequentially formed on a bottom shield in a read head.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: August 24, 2010
    Assignee: Headway Technologies, Inc.
    Inventors: Tong Zhao, Kunliang Zhang, Hui-Chuan Wang, Yu-Hsia Chen, Min Li
  • Publication number: 20100195369
    Abstract: A data storage system comprises first and second storage layers, a reader and a writer. The first storage layer has a first coercive potential and a first polarization. The second storage layer has a second coercive potential that is less than the first coercive potential, and a second polarization that is coupled to the first polarization. The writer performs a write operation in which a write potential is imposed across the first and second storage layers, such that the first coercive potential is exceeded across the first storage layer and the second coercive potential is exceeded across the second storage layer. The reader performs a read operation in which a read potential is imposed across the first and second storage layers, such that the second coercive potential is exceeded across the second storage layer and the first coercive potential is not exceeded across the first storage layer.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Tong Zhao, Martin Gerard Forrester, Florin Zavaliche, Joachim Ahner
  • Publication number: 20100187583
    Abstract: A reconfigurable electric circuit includes first and second crystalline material layers positioned adjacent to each other and forming a first interface, and a first ferroelectric layer positioned adjacent to the first crystalline material layer and having ferroelectric domains applying an electric field to regions of the first interface to induce a quasi two-dimensional electron gas in the regions, wherein at least one of the regions forms a gate and at least one of the regions forms a channel.
    Type: Application
    Filed: January 26, 2009
    Publication date: July 29, 2010
    Applicant: Seagate Technology LLC
    Inventors: Stephen John Wrazien, Florin Zavaliche, Joachim Walter Ahner, Tong Zhao, Martin Gerard Forrester, Shan Hu
  • Publication number: 20100188773
    Abstract: A data storage medium that includes a multiferroic thin film and ferromagnetic storage domains formed in the multiferroic thin film. The multiferroic thin film may be formed of at least one of BiFeO3, or any other ferroelectric and antiferromagnetic material. The ferromagnetic storage domains may be formed in the multiferroic thin film by an ion implantation process. A data storage system that incorporates the data storage medium is also provided.
    Type: Application
    Filed: January 29, 2009
    Publication date: July 29, 2010
    Applicant: Seagate Technology LLC
    Inventors: Florin Zavaliche, Tong Zhao, Philip George Pitcher, Michael Allen Seigler