Abstract: Implementations of the present disclosure are directed to systems and methods for reducing design complexity and critical path timing challenges of credit return logic. A wide bus supports simultaneous transmission of multiple flits, one per lane of the wide bus. A source device transmitting flits on a wide bus selects from among multiple credit return options to ensure that only one of the multiple flits being simultaneously transmitted includes a credit return value. In some example embodiments, the receiving device checks only the flit of one lane of the wide bus (e.g., lane 0) for credit return data. In other example embodiments, the receiving device uses a bitwise-OR to combine the credit return data of all received flits in a single cycle.

Abstract: Implementations of the present disclosure are directed to systems and methods for mapping point-to-point channels to packet virtual channels. A chip with an point-to-point interface converts point-to-point data to a packet format. The point-to-point channels are mapped to virtual channels of the packet transmission protocol. Information from multiple point-to-point channels may be combined in a single packet. Among the benefits of implementations of the present disclosure is that point-to-point devices may be connected to a packetized network without losing the benefits of separate channels for different types of communication. This allows existing point-to-point devices to communicate using a packetized network without internal modification or performance degradation.

Abstract: Devices and techniques for programmable atomic operator resource locking are described herein. A request for a programmable atomic operator (PAO) can be received at a memory controller that includes a programmable atomic unit (PAU). Here, the request includes an identifier for the PAO and a memory address. The memory addressed is processed to identify a lock value. A verification can be performed to determine that the lock value indicates that there is no lock corresponding to the memory address. Then, the lock value is set to indicate that there is now a lock corresponding to the memory address and the PAO is invoked based on the identifier for the PAO. In response to completion of the PAO, the lock value is set to indicate that there is no longer a lock corresponding to the memory address.

Abstract: Devices and techniques for self-scheduling threads in a programmable atomic unit are described herein. When it is determined that an instruction will not complete within a threshold prior to insertion into a pipeline of the processor, a thread identifier (ID) can be passed with the instruction. Here, the thread ID corresponds to a thread of the instruction. When a response to completion of the instruction is received that includes the thread ID, the thread is rescheduled using the thread ID in the response.

Abstract: Implementations of the present disclosure are directed to systems and methods for processing headers that support multiple protocols. A header of a packet includes a bridge type (BTYPE) field that indicates the protocol of the packet. A command field of the packet is interpreted differently based on the value of the BTYPE field. Among the benefits of implementations of the present disclosure is that a single network may be used to carry packets of different protocols without the overhead of encapsulation.

Abstract: Disclosed in some examples, are methods, systems, programmable atomic units, and machine-readable mediums that provide an exception as a response to the calling processor. That is, the programmable atomic unit will send a response to the calling processor. The calling processor will recognize that the exception has been raised and will handle the exception. Because the calling processor knows which process triggered the exception, the calling processor (e.g., the Operating System) can take appropriate action, such as terminating the calling process. The calling processor may be a same processor as that executing the programmable atomic transaction, or a different processor (e.g., on a different chiplet).

Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A primary device coupled to the SPI bus can generate read or write instructions for a secondary device. In response to instructions from the primary device, the secondary device can prepare a response. The response message can include a secondary device status field to indicate a readiness of the secondary device to provide a particular data payload to the primary device. Using deferrals that are communicated from the secondary device to the primary device can enable longer latency SPI operations to proceed without monopolizing the SPI bus.

Abstract: Devices and techniques for variable pipeline length in a barrel-multithreaded processor are described herein. A completion time for an instruction can be determined prior to insertion into a pipeline of a processor. A conflict between the instruction and a different instruction based on the completion time can be detected. Here, the different instruction is already in the pipeline and the conflict detected when the completion time equals the previously determined completion time for the different instruction. A difference between the completion time and an unconflicted completion time can then be calculated and completion of the instruction delayed by the difference.

Abstract: Implementations of the present disclosure are directed to systems and methods for flow control using a multiple flit interface. A credit return field is used in a credit-based flow control system to indicate that one or more credits are being returned to a sending device from a receiving device. Based on the number of credits available, the sending device determines whether to send device or wait until more credits are returned. The amount of buffer space used by the receiver to store the packet is determined by the number of transfer cycles used to receive the packet, not the number of flits comprising the packet. This is enabled by having the buffer be as wide as the bus. The receiver returns credits to the sender based on the number of buffer rows used to store the received packet, not the number of flits comprising the packet.

Abstract: Disclosed in some examples, are methods, systems, programmable atomic units, and machine-readable mediums that provide an exception as a response to the calling processor. That is, the programmable atomic unit will send a response to the calling processor. The calling processor will recognize that the exception has been raised and will handle the exception. Because the calling processor knows which process triggered the exception, the calling processor (e.g., the Operating System) can take appropriate action, such as terminating the calling process. The calling processor may be a same processor as that executing the programmable atomic transaction, or a different processor (e.g., on a different chiplet).

Abstract: Devices and techniques for threads in a programmable atomic unit to self-schedule are described herein. When it is determined that an instruction will not complete within a threshold prior to insertion into a pipeline of the processor, a thread identifier (ID) can be passed with the instruction. Here, the thread ID corresponds to a thread of the instruction. When a response to completion of the instruction is received that includes the thread ID, the thread is rescheduled using the thread ID in the response.

Abstract: A system may include multiple electronic devices and multiple hardware transceivers. The multiple electronic devices may be coupled to each other via an interface network, and may include multiple chiplets. The multiple hardware transceivers, with at least one transceiver included in or coupled to a respective electronic device of the multiple electronic devices, may each be configured to receive data packets from a source device. The data packets may each include a path field including path information indicating a path to a destination device and a bridge-type field including bridge-type information indicating a type of the path information in the path field. The source device and the destination device may each include a chiplet. The multiple hardware transceivers may each be further configured to transmit the received data packets to the destination device using the path information and the bridge-type information of each received data packet.

Abstract: A transmitting device generates multiple small packets for a large packet and transmits them to a receiving device. Routing devices forward the multiple small packets to the receiving device. Each of the smaller packets, except the last packet, has a sequence indicator set. As a result, the receiving device is able to determine that each of the smaller packets is part of a larger packet and buffer the smaller packets or their payloads. When the last packet is received, the larger packet is complete and may be processed by the receiving device. The routing devices delay requests from other transmitting devices to transmit data to the receiving device until the last packet is sent to the receiving device. The routing devices may continue to route traffic to the receiving device on all virtual channels other than a virtual channel being used for the large packet.

Abstract: Chiplet systems may include a memory controller that has programmable atomic units that execute programmable atomic transactions. These instructions are stored in one or more memory partitions of memory in the programmable atomic unit. Since the programmable atomic unit executes programmable atomic transactions that are customized for various processes, and since the programmable atomic unit is a physical resource shared by multiple processes, the processes need a way of both loading the programmable atomic unit memory with instructions and a method of calling those instructions. Disclosed are methods, systems, and devices for registering, calling, and virtualizing programmable atomic transactions.

Abstract: Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.

Abstract: Chiplet systems may include a memory controller that has programmable atomic units that execute programmable atomic transactions. These instructions are stored in one or more memory partitions of memory in the programmable atomic unit. Since the programmable atomic unit executes programmable atomic transactions that are customized for various processes, and since the programmable atomic unit is a physical resource shared by multiple processes, the processes need a way of both loading the programmable atomic unit memory with instructions and a method of calling those instructions. Disclosed are methods, systems, and devices for registering, calling, and virtualizing programmable atomic transactions.

Abstract: A chiplet system comprises an interposer including interconnect and multiple chiplets arranged on the interposer and interconnected using the interconnect of the interposer. The multiple chiplets include a throttle level bus source chiplet including a throttle level bus drive interface configured to place a throttle level value onto the throttle level bus, and one or more throttle level bus receiver chiplets operatively coupled to the throttle level bus. Each chiplet of the multiple chiplets includes throttling logic circuitry configured to set a throttle level of a chiplet according to the throttle level value.

Abstract: Devices and techniques for communicating a programmable atomic operator to a memory controller are described herein. A memory controller can receive a memory request and extract a command indicator that indicates a programmable atomic operator (PAO) command from the memory request. The memory controller can then extract a PAO index from the request and invoke the PAO based on the PAO index.

Abstract: Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.

Abstract: Devices and techniques for programmable atomic operator resource locking are described herein. A request for a programmable atomic operator (PAO) can be received at a memory controller that includes a programmable atomic unit (PAU). Here, the request includes an identifier for the PAO and a memory address. The memory addressed is processed to identify a lock value. A verification can be performed to determine that the lock value indicates that there is no lock corresponding to the memory address. Then, the lock value is set to indicate that there is now a lock corresponding to the memory address and the PAO is invoked based on the identifier for the PAO. In response to completion of the PAO, the lock value is set to indicate that there is no longer a lock corresponding to the memory address.